﻿ Digital Circuits and Systems - Circuits i Sistemes Digitals (CSD) - EETAC UPC
 Bachelor's Degree in Telecommunications Systems and in Network Engineering

## CSD products

This is a detailed list of materials for helping you to study and design projects and thus, passign the course without complications. Please, get used to ask us as many questions as necessary.

 Analysis and design tutorials Analysis and design assignments Questions Exam 1 Exam 2 Assessment

### Chapter 1 analysis of circuits based on logic gates:

 AT1.1 Circuit_C (P1) Circuit_W, (Lab1.1) Circuit_W, (Lab1.2) AT1.4 Circuit_K AT1.5 Circuit_P AT1.6 Circuit_Q

### Chapter 2 analysis of circuits based on flip-flops and logic:

 AT2.1 Circuit_Async, (Lab5) AT2.2 Circuit_Sync1 (update) AT2.3 Circuit_Async2  (P5) AT2.4 Circuit_Async4  (update)

 Analysis and design tutorials Analysis and design assignments Questions Exam 1 Exam 2 Assessment

### Chapter 1 and 3 design projects of combinational circuits

In Chapter 3 these circuits are used to learn basic digital input and output.

### Chapter 2 and 3 design tutorials on FSM

Design tutorials of sequential circuits (FSM) plan C1. In Chapter 3 these circuits are used for learning interrupts and microcontroller applications:

 DT6.1 D_FF , D-type flip-flop DT6.2 JK_FF, JK flip-flop (also an RS-flip-flop) DT6.3 T_FF, Toggle flip-flop DT6.4 Matrix_encoder_16key  (P6) DT6.5 Light_control, classroom luminaries, (Lab6) DT6.6 LED bicycle torch DT6.7 Debouncing_filter, low-pass filter and synchroniser. DT6.8 Traffic light controller DT10.1 Design phase #1 Serial_transmitter (P10) DT11.2 Design phase #2 Serial_transmitter_LCD (P11) DT12.1 Design phase #3 Serial_transmitter_LCD_TMR0 (P12) DT12.2 Design phase #4 Serial_transmitter_LCD_TMR2

### Chapter 2 and 3 design tutorials on counters and registers

 Plan X: FSM, state enumeration Plan Y: FSM, large number of states Plan C2: hierarchical structure DT7.1 DT10.2 Counter_BCD_1digit, (Lab10), (design phase #1) DT11.3 (design phase #2) DT12.3 Counter_BCD_1digit_LCD_TMR0 (design phase #3) where TMR0 as counter replaces INT0. DT10.3 Counter_mod_1572, (Lab10) DT7.2 , (Lab7) , (Lab7) DT7.3 Counter_mod16 (versatile chip) DT7.4 Hour_counter (P7) DT7.5 DT7.6 Data_reg_4bit DT7.7 Shift_reg_4bit DT10.4 Johnson_sequencer_mod12 (design phase #1) DT11.4 Johnson_sequencer_mod12_LCD (design phase #2) DT12.4 Johnson_sequencer_mod12_LCD_TMR0 (design phase #3) DT7.7 counter_BCD_2digit.pdsprj  (modulo 100) in Proteus, plan C2, chaining two 1-digit BCD counters

### Chapter 2 and 3 design tutorials on dedicated processors

 DT8.1 Timer_MMSS (P8) Timer_MMSS DT8.2 Mult_4bit serial multiplier DT8.3 Adder_4bit serial adder DT8.4 USART universal serial async receiver & transmitter DT12.5 Design phase #1 Timer, (Lab11) DT12.6 Design phase #2 , (Lab11) DT12.7 Design phase #3 , (Lab11) DT12.8 Design phase #4 DT12.9 (Arduino) DT12.10 (Arduino)

 Analysis and design tutorials Analysis and design assignments Questions Exam 1 Exam 2 Assessment

### Chapter 1 analysis assignments

 Circuit_L A1.2 Circuit_U A1.3 Circuit_VT A1.4 Circuit_M Circuit_N Circuit_G Circuit_R Circuit_Z Circuit_Y

### Chapter 2 analysis assignments

 Circuit_E (sync) A2.2 Circuit_A  (async) A2.3 Circuit_D  (async) A2.4 Circuit_I  (async) Circuit_F (sync) Circuit_B  (async) Circuit_C  (async) A2.8 Circuit_G  (async) A2.9 Circuit_H  (async)

 Analysis and design tutorials Analysis and design assignments Questions Exam 1 Exam 2 Assessment

### Chapter 1 and 3 design assignments

 Wind compass D1.2 B3.2 BCD_7seg_decoder chip D1.3 B3.3 5-bit ones counter D1.4 From P1: Circuit_VT, Circuit_G, Circuit_U D1.5 8-bit subtractor using Subtractor_1bit Water tank level meter (9 sensors) D1.7 B3.7 DeMUX_16, DeMUX_8 D1.8 B3.8 16-bit/8-bit comparator for base-2 numbers 16-bit comparator for integer numbers Parking occupancy (32-bit ones counter) B3.11 Sel _add_subt_comp_10bit B3.12 5-bit Gray to binary converter B3.13 12-to-4 encoder, 8-to-3 encoder D1.14 9-bit parity generator, parity checker D1.15 BCD_bin_3digit, code converter D1.16 Bin_BCD_9bit, code converter D1.17 2-digit BCD adder D1.18 ALU_12bit D1.19

### Chapter 2 and 3 design assignments

 CD player buttons D2.2 D3.2 Stepper motor controller D2.3 D3.3 Designing a LED rotator D2.4 D3.4 Pattern detector (versions 1 and 2) LED dimmer 7-segment digit sequencer Dumbwaiter or simple lift Electronic keypad lock (versions A and B) Water tank controller Vending machine D2.11 Wireless IR TV remote control Electronic roulette 3-digit programmable BCD down counter Traffic light controller 16-key matrix encoder with handshake D2.16 Scale (BCD up counter modulo 50000) Shower stall automation Morse code generator Washing machine controller D2.20 D3.20 Chip 74HC4017 (5-bit Johnson counter) D2.21 Programmable timer D2.22 D3.22 Bit pattern generator D2.23 Earbuds control buttons D2.24 Rotation speed meter (tachometer)

### Laboratory prototypes and PCB for soldering and measuring

Circuit_W (Lab1_2), MUX_DeMUX (Lab2), Dec_Hex_7seg (DE10-Lite), ALU_9bit (Lab4), .

 Analysis and design tutorials Analysis and design assignments Questions Exam 1 Exam 2 Assessment

- Sample questionnaire Q1_4 on P1, P2, P3 and P4 projects.

- Sample questionnaire Q5_8 on P5, P6, P7 and P8 (content from all previous projects is included).

- Sample questionnaire Q9_12 on P9, P10, P11 and P12 projects (content from all previous projects is included).

 Analysis and design tutorials Analysis and design assignments Questions Exam 1 Exam 2 Assessment

- 2324Q2 pdf and solution ideas.

- 2324Q1 pdf and solution ideas. Prob1 circuit in Proteus.

- 2223Q2 pdf and solution ideas.

- 2223Q1 pdf and example solutions.

- 2122Q2 pdf and example solutions Prob1, Prob2.

- 2122Q1 pdf and example solutions. Prob1 and Prob4 in Proteus.

- 2021Q2 pdf and example solutions. Prob1 in Proteus (Version 8.12)

- 2021Q1 pdf and example solutions.

- 1920Q1 pdf and example solutions.

- 1819Q2 pdf and example solutions (Prob. 1 option B is here as the Circuit_Q).

- 1819Q1 pdf and discussed solutions (Prob1) (Prob2).

- 1718Q2 pdf and a discussed solution. This is the Problem 1 truth table in Minilog format.

- 1718Q1 pdf and a Proteus simulation  to experiment the way it works, and a possible solution. The Gray_Bin_Converter (Chip1) in Minilog format.

- 1617Q2 pdf that contains many concepts develop since now through P1 .. P4. This is the Proteus file, the truth table in Minilog and the results when simplifying by PoS.

- 1617Q2 pdf. The truth table and the symbol in Proteus that can be simulated attaching this "jed" to the AM22V10 sPLD. This is a VHDL file using plan B (question 5), and this is the ispLEVER Classic report where you see the pin connections after synthesising the circuit.

 Analysis and design tutorials Analysis and design assignments Questions Exam 1 Exam 2 Assessment

- 2324Q2 pdf and solution ideas. P1 in Proteus (method II).

- 2324Q1 pdf and solution ideas. P1 analysis (method I). P1 in Proteus (method II) to check the analytical result and edited printed output waves.

- 2223Q2 pdf and solution ideas. Question 10 async circuit in Proteus.

- 2223Q1 pdf and solution ideas. Prob1 in Proteus to check the analytical result.

- 2122Q2 pdf and solution ideas.

- 2122Q1 pdf and example solutions. Prob1 in Proteus. P1 in VHDL.

- 2021Q2 pdf and example solutions. Prob1 in Proteus.

- 2021Q1 pdf and example solutions (Prob1 - Proteus, Prob2, and Prob3 - Proteus).

- 1920Q2 pdf and example solutions.

- 1920Q1 pdf and example solutions.

- 1819Q2 pdf and example solutions (Prob1-Prob2) (Prob3, this is a tutorial solution on specifications and planning, like class notes. This is an example project in Proteus for the serial transmitter (Circuit, waves. This Prob3 is a kind of introduction for projects such N.15 where the USART peripheral is used for serial RS232 transmissions).

- 1819Q1 pdf and example solutions (Prob1) (Prob2).

- 1718Q2 pdf and a draft solution example (Prob1, Prob2, Prob3).

- 1718Q1 pdf and a draft solution example.

 Analysis and design tutorials Analysis and design assignments Questions Exam 1 Exam 2 Assessment

### Continuous assessment of student achievement

CSD scheme of continuous assessment (grading sheet): 17 items, 11 of which include weekly formative feedback and discussion. Your partial grades will be available and updated at Atenea platform.

• P_Ch1 => 10%, (10%) + PLA1.2 (10%) + PLA2 (20%) + PLA3 (teamwork, report + video, 50%) + (10%)

• P_Ch2 => 10%, (20%) + PLA6 (30%) + PLA7 (teamwork, report + video, 50%)

• P_Ch3 => 10 %, (20%) + PLA10 (30%) + (teamwork, work in progress + report + video, 50%)

• Classroom activities => 8%

• EXA1 => 25%; EXA2 => 25%

• Q1-4 => 4%; Q5-8 => 4%; Q9-12 => 4%