UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL
 

CSD exams, problems, questions and assessment mechanism

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Projects

P_Ch1, P_Ch2 and P_Ch3 are submitted during the course planned as post-lab assignments (PLA). Most of PLA are adapted from exam problem listed below.

Problems

Chapter 1 analysis: A1.1 A1.2 A1.3 A1.4 A1.5 A1.6 A1.7    
Chapter 1 designs: D1.1 D1.2 D1.3 D1.4 D1.5 D1.6 D1.7 D1.8 D1.9 D1.10
  D1.11                    

 

Chapter 2 analysis: A2.1 A2.2 A2.3 A2.4 A2.5 A2.6 A2.7 A2.8  
Chapter 2 designs: D2.1 D2.2 D2.3 D2.4 D2.5 D2.6 D2.7 D2.8 D2.9 D2.10  
D2.11 D2.12 D2.13 D2.14 D2.15 D2.16 D2.17 D2.18 D2.19 D2.20
  D2.21 D2.22 D2.23                

 

Chapter 3 μC basics: B3.1 B3.2 B3.3 B3.4 B3.5 B3.6 B3.7    
Chapter 3 designs: D3.1 D3.2 D3.3 D3.4 D3.5 D3.6 D3.7 D3.8 D3.9 D3.10
D3.11 D3.12 D3.13 D3.14 D3.15 D3.16 D3.17 D3.18 D3.19 D3.20
    D3.22                  

Questions and controls

- Sample questionnaire Q1_4 on P1, P2, P3 and P4 projects.

- Sample questionnaire Q5_8 on P5, P6, P7 and P8 (content from all previous projects is included).

- Sample questionnaire Q9_12 on P9, P10, P11 and P12 projects (content from all previous projects is included).

Examples of mid-term exams  (EXA1)

- 2223Q2 pdf and solution ideas.

- 2223Q1 pdf and example solutions.

- 2122Q2 pdf and example solutions Prob1, Prob2.

- 2122Q1 pdf and example solutions. Prob1 and Prob4 in Proteus.

- 2021Q2 pdf and example solutions. Prob1 in Proteus (Version 8.12)

- 2021Q1 pdf and example solutions.

- 1920Q1 pdf and example solutions.

- 1819Q2 pdf and example solutions (Prob. 1 option B is here as the Circuit_Q).

- 1819Q1 pdf and discussed solutions (Prob1) (Prob2).

- 1718Q2 pdf and a discussed solution. This is the Problem 1 truth table in Minilog format. 

- 1718Q1 pdf and a Proteus simulation  to experiment the way it works, and a possible solution. The Gray_Bin_Converter (Chip1) in Minilog format.

- 1617Q2 pdf that contains many concepts develop since now through P1 .. P4. This is the Proteus file, the truth table in Minilog and the results when simplifying by PoS.

- 1617Q2 pdf. The truth table and the symbol in Proteus that can be simulated attaching this "jed" to the AM22V10 sPLD. This is a VHDL file uisng plan B (question 5), and this is the ispLEVER Classic report where you see the pin connections after synthesising the circuit.

Examples of final-term exams  (EXA2)

- 2223Q1 pdf and solution ideas. Prob1 in Proteus to check the analytical result.

- 2122Q2 pdf and solution ideas.

- 2122Q1 pdf and example solutions. Prob1 in Proteus. P1 in VHDL.

- 2021Q2 pdf and example solutions. Prob1 in Proteus.

- 2021Q1 pdf and example solutions (Prob1 - Proteus, Prob2, and Prob3 - Proteus).

- 1920Q2 pdf and example solutions.

- 1920Q1 pdf and example solutions.

- 1819Q2 pdf and example solutions (Prob1-Prob2) (Prob3, this is a tutorial solution on specifications and planning, like class notes to reach a deep insight into to project and be able to develop and test it almost effortless. This is an example project in Proteus for the serial transmitter (Circuit, waves. This Prob3 is a kind of introduction in case you have to solve a P_Ch3 project like the N. 13 whre the USART peripheral is user for serial RS232 transmissions). 

- 1819Q1 pdf and example solutions (Prob1) (Prob2).

- 1718Q2 pdf and a draft solution example (Prob1, Prob2, Prob3).

- 1718Q1 pdf and a draft solution example.

Assessment of student achievement 

CSD scheme of continuous assessment. Your partial grades will be available at Atenea platform.