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CSD exams, questions and assessment mechanism |
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In this course practically all lecturing, laboratory, guided activities and study time is for solving projects in this fashion as if you already were a professional engineer:
1. Specifications, 2. Planning, 3. Development, and 4. Test.
You are encouraged to write reports for the designed circuits, finishing as much exercises as you can and show them to us for correction and discussion. Because writing original reports is the best way to learn deeply the course content and put into practice cross-curricular skills.
- Sample questionnaire Q1_4 on P1, P2, P3 and P4 projects.
- Sample questionnaire Q5_8 on P5, P6, P7 and P8 (remember that P1, P2, P3 and P4 are also included).
- Sample questionnaire Q9_12 on P9, P10, P11 and P12 projects (remember that content from all previous projects is also included).
These are former assignment collections in PDF posted as additional study materials. We will translate them into web pages for easy browsing. Chapter 1: combinational circuits. Chapter 2: sequential systems. Chapter 3: microcontroller applications
Current laboratory projects.
Former laboratory projects kept only for reference purposes:
2021Q2, 2021Q1, 1920Q2, 1920Q1
- 2122Q1. This is the exam EX1 (pdf) and example solutions. P1 and P4 in Proteus.
- 2021Q2. This is the exam EX1 (pdf) and example solutions. P1 in Proteus (Version 8.12)
- 2021Q1. This is the exam EX1 (pdf) and example solutions.
- 1920Q1. This is the exam EX1 (pdf) and example solutions.
- 1819Q2. This is the exam EX1 (pdf) and example solutions (Prob. 1 option B is here as the Circuit_B).
- 1819Q1. This is the exam EX1 (pdf) and discussed solutions (P1) (P2).
- 1718Q2. This is the exam EX1 (pdf) and a discussed solution. This is the Problem 1 truth table in Minilog format.
- 1718Q1. This is the exam EX1 (pdf) and a Proteus simulation to experiment the way it works, and a possible solution. The Gray_Bin_Converter (Chip1) in Minilog format.
- 1617Q2. This is an example exercise IT1 (pdf) that contains many concepts develop since now through P1 .. P4. This is the Proteus file, the truth table in Minilog and the results when simplifying by PoS. This is the discussion on the problem solved some years ago.
- 1617Q2. This is another similar exercise IT1r (pdf). The truth table, the Minilog result, and the symbol in Proteus that can be simulated attaching this "jed" to the AM22V10 sPLD. This is a possible VHDL file (question 5), and this is the ispLEVER Classic report where you see the pin connections after synthesising the circuit.
- 2021Q2. This is the exam EX2 (pdf) and example solutions. P1 in Proteus.
- 2021Q1. This is the exam EX2 (pdf) and example solutions (P1 - Proteus, P2, and P3 - Proteus).
- 1920Q2. This is the exam EX2 (pdf) and example solutions.
- 1920Q1. This is the exam EX2 (pdf) and example solutions.
- 1819Q2. This is the exam EX2 (pdf) and example solutions (P1-P2) (P3, this is a tutorial solution on specifications and planning, like class notes to reach a deep insight into to project and be able to develop and test it almost effortless. This is an example project in Proteus for the serial transmitter (Circuit, waves. This P3 is a kind of introduction in case you have to solve a P_Ch3 project like the N. 13 whre the USART peripheral is user for serial RS232 transmissions).
- 1819Q1. This is the exam EX2 (pdf) and example solutions (P1) (P2).
- 1718Q2. This is the exam EX2 (pdf) and a draft solution example (P1, P2, P3).
- 1718Q1. This is the exam EX2 (pdf) and a draft solution example.
CSD scheme of continuous assessment. Your partial grades will be available at Atenea platform.
P_Ch1 => 10% ; P_Ch2=> 10%; P_Ch3 => 15 %
EXA1 = 25%; EXA2 = 25%
Q1_4 = 5% ; Q5_8 = 5% ; Q9_12 = 5%