upc eetac_1

P7

P_Ch2 - Project P8 on a keypad-controlled  timer

P9


CLK generators and hardware dedicated processors

1. Specifications

Let's connect components developed using P6 and P7 techniques to generate a timer circuit that can count down up to one hour real-time (Timer_MMSS). At the same time we'll develop some ideas on the CLK_generator component to derive all the CLK signals from the same external quartz crystal oscillator.

This project, as the last one in this Chapter II, is going to be solved more autonomously. You have to try to organise the general architecture of the Timer_MMSS in Fig. 1.

Timer_MMSS

Fig 1. Symbol and the main details of the Timer_HHMM.  

System specifications:

- This is a complex project which requires teamwork, project and time management and English.

- Specifications for the Xilinx Nexys 2 FPGA Board  or the Altera terasic DE0 Board board.

- This is the same project (Proteus) solved using Chapter 3 tools and microcontrollers for demonstration purposes. Unzip both files in the same folder and run the simulation. The flicking of the displays is a simulator issue which doesn't accur in a real prototype.

 

Learning materials

Learning materials and tutorials on how to design large frequency dividers: 

- On the design of a large synchronous frequency divider with many pulsed and squared outputs generated from a high frequency crystal quartz oscillator. Here you are the bicycle LED torch (P6) with its internal CLK_Generator circuit.

- This is a complete example of a HH:MM:SS digital clock solved in Proteus and based on sPLD. Simply unzip the files in a folder and run the simulation.

- Study other similar dedicated processors to comprehend how a dedicated processor architecture can be applied once and again in a very diversified set of applications based on hardware design. Naturally, many of these application can be redesigned using a software-based microcontroller, which is the aim of the next P9 projects.

 

2. Planning (Devising a strategy to solve the problem)

Organise the hierarchical architecture discussed in class and represented in Fig. 2. This large project must be solved in several steps using teamwork.

Dedicated processor

Fig. 2. General plan for a dedicated processor, which is the key for solving complex digital systems. Many applications can be inferred using this plan: data transmitters and receivers, A/D and D/A converters, digital filters, timers, etc. Many microcontroller subsystems or peripherals are planned in this way.

The datapath is charge of performing operations with the information while the control unit is in charge of  sequencing the algorithm or the flowchart.

A CLK generator is required because most of the times several synchronous CLK signals derived form a quartz crystal are required.

- This is the idea of the dedicated processor applied to the Timer_HHMM.  

- This is the idea of the datapath (1) and (2).  This is the component BCD_Counter_mod60  (visio), which can be used twice for implementing the Counter_MMSS for counting seconds and minutes. 

- This is the idea of the control unit

- Deriving signals from crystal oscillators: CLK generator as hierarchical circuit (plan Z). We’ll learn how it works chaining frequency dividers (freq_div_Mod, plan Y) and T_FF for squaring the waveforms. The objective is to build this circuit below in order to generate all the necessary squared waveforms for the Timer_MMSS.

CLK_GEN

Fig. 3. Symbol of the CLK_Generator require for the Timer_MMSS.

 This is how you can divide the CLK frequency by a given number N and the way to square the signal using a T_FF. And this is the idea of the complete CLK_generator circuit to be used in an Altera DE0 board or a Digilent Nexys 2 board that includes a 50 MHz oscillator.

DE0 oscillator

Fig. 4.  Altera DE0 board 50 MHz oscillator from which we'll derive the synchronous squared CLK signals of: 100 kHz, 1.6 kHz, 20 Hz, and 1 Hz required in this project.

Therefore, from these discussions and sketches we hope that you will be able to draw a complete schematic, fully annotated in order to continue with the development of each chip.

3. Developing

1.- Synthesise and test the CLK_generator.  This is an example file which can be in this problem:  a freq_div_25.vhd. Modify it conveniently to generate other similar components. Thus, organise the complete CLK_Generator using frequency dividers and T_FF to square the pulsed waveforms.  

While examining the EDA results, the RTL schematic, be aware of the number of registers (D_FF) used in the target chip and justify the value. Does it match with your initial estimation?


2.- Synthesise the Datapath. For instance:

Go back to P7 and :

A.- Learn how the component Counter_mod16 works. It is necessary to perfectly comprehend this component and their many features before using it for some purpose. You have it all designed as a tutorial and you can play even with it using the simulator Proteus or the real board in the lab.

B.- Study carefully the Hour_Counter example in P7.

Finally: 

C.- Truncate the previous counter, because your main goal is to produce a BCD_Counter_mod60.

D.- And now the Counter_mod3600 and the other elements in the datapath.

Be aware of the number of registers (D_FF) used in the target chip and justify the value. Does it match with your initial estimation?


3.- Synthesise the Control_unit. Assemble all the circuit  Timer_MMSS. This time, it is far better to complete the circuit and test it all together tricking the CLK_Generator to speed up simulations. 

 

- Here you are the complete project Timer_HHMM solved for a NEXYS2 board as a reference for studying such complex projects.

4. Testing 

Complete the template test bench file and run the EDA tool.

Hint: in case of simulating the CLK_Generator as a component, because it is about counting tens of milions of pulses, there is a way to speed up the simulatiuon tricking the frequency dividers while keeping the number of registers used and everything else, as shown in Fig. 4. The output waveforms will be of different frequencies, but they will be synchronous and identical as in the real CLK_Generator which has to be configured in the real hardware. 

Spped
 Fig. 4. Modification in the VHDL code to speed up the simulations of the CLK_Generator component. 

 

Print some timing diagrams and analyse that the circuit works fine in all situations.

 

5. Report

Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources .

Remember that in class you'll be required to explain any section of your project individually or in group.

 

6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works.

 

Other similar projects on sequential circuits

Here you are some examples of former complete projects involving many VHDL files in a similar hierarchical architecture. The same robust and clear design procedures has been applied once and again gaining reliability and know-how:

- Serial adder (ref.)

- Serial multiplier (ref.)

- USART subsystem to transmit and receive asynchronous data (ref.)

- This is a final project on a traffic light controller.

- This is the planning of a programmable timer.

- This is the planning of a programmable timer controlled using a keypad.

 

- Exams, questions, problems and projects. In case that this P_Ch2 project had to be assessed, here you are an organization and assessment checklist.

 

Other materials of interest

 Up to this point in the course, you've learned what represents the basics of hardware design of modern digital systems. No doubt that you can continue this subject's content designing with hardware tools and VHDL more advanced systems and even microprocessors and microcontrollers. However, the chapter 3 of this introductory CSD course will be based on the use of a commercial microcontroller precisely to repeat some previous project but from the software point of view.