UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL


P8: Dedicated processors (datapath, control unit, CLK generator)


Resources in lectures and labs: L8 on dedicated processors and CLK generators. Project objectives

Highlighted projects: MM:SS programmable timer, CLK generator

1. Specifications

The idea is to invent a timer circuit (Timer_MMSS) that can count down up to one hour real-time. Additionally, we will develop some ideas on the component CLK_generator to derive all the system synchronous CLK signals from the same external quartz crystal oscillator.


Fig 1. Front panel with main details of the Timer_MMSS application.

Circuit's symbol is shown in Fig. 2.


Fig 1. Symbol and signal naming.

The complete set of specifications and an example of timing diagram is represented in Fig. 3.

Fig 3. Specifications and example timing diagram.

- This is a complex project that requires putting into practise: teamwork (1), project and time manegement (2) and English (4).

- This project, as the last one in this Chapter II, is going to be solved more autonomously: organise the general architecture of the Timer_MMSS in Fig. 1 as a dedicated processor.

- Target boards and programmable chips: Xilinx Nexys 2 FPGA board or Intel Terasic DE0 Board board. 

This is the same project Timer_MMSS in Proteus solved for demonstration purposes using Chapter 3 P12 tools and microcontrollers. Unzip both files in the same folder and run the simulation. Display flicking is a simulator issue that does not occur in a real prototype.


Other similar projects:

As usual, we recommend analysing tutorials to get enough experience to tackle this Timer_MMSS project. All these projects are based on dedicated processor architecture.

Serial 4-bit multiplier

 Traffic light controller (enhanced version from P6),

 Programmable timer,

 Programmable timer controlled using a keypad,

Serial 4-bit adder


Other ideas for future CSD projects: stepper motor controller, tachometer, frequency and period meter, successive aproximation A/D converter, signal generator, etc.


2. Planning

Organise the hierarchical architecture represented in Fig. 4 that represents the general framework of an advanced digital system or dedicated processor. This large project is better solved in several steps using teamwork.

Dedicated processor

Fig. 4. General plan for a dedicated processor, which is the key for solving complex digital systems. Many applications can be inferred using this plan: data transmitters and receivers, A/D and D/A converters, digital filters, timers, etc. Many microcontroller subsystems or peripherals are planned in this way.

The datapath is in charge of performing operations with the information while the control unit is in charge of  sequencing the algorithm or the flowchart.

A CLK generator is recessary because several synchronous CLK signals with different frequencies derived form the same quartz crystal are required.

Some additional details on the idea of a dedicated processor applied to this project Timer_MMSS.  

Dedicated processor
Fig 5. Main blocks on the dedicated processor.

Datapath components. Basically for a counting capacity up to 3600 in BCD.

datapath details
Fig 6. Datapath.

This is the idea of the datapath (1) and discussion of other circuit details.

Counter Counter

Fig 7. Counter symbols used in the datapath (visio). Counter_MMSS includes Counter_BCD_mod60 blocks for counting seconds and minutes.


Control unit.  The idea and state diagram is sketched in Fig.

Fig 8. Control unit symbol, signals and state diagram ideas to organise the FSM.

CLK generator as hierarchical circuit (plan C2). We will learn how it works chaining frequency dividers (freq_div_Mod, plan Y) and T_FF for squaring the waveforms. The objective is to build this circuit below in order to generate all the necessary squared waveforms for the Timer_MMSS.


Fig. 9 Symbol of the CLK_Generator required for the Timer_MMSS.

In Fig. 9 there is the architecture of the complete CLK_Generator circuit to be used in an Intel DE0 board or a Digilent Nexys 2 board that includes a 50 MHz oscillator. Is is adapted from this unit.

CLK Generator
 Fig. 10. Modification in the VHDL code to speed up the simulations of the CLK_Generator component. 

Fig 11 shows a picture of the 50 MHz  quartz crystal populating the Altera DE0.

DE0 oscillator

Fig. 11.  Altera DE0 board 50 MHz oscillator from which we'll derive the synchronous squared CLK signals of: 100 kHz, 1.6 kHz, 20 Hz, and 1 Hz required in this project.

Therefore, from these discussions and sketches we hope that you will be able to draw a complete schematic, fully annotated in order to continue with the VHDL development of each chip and top entity. Some additional notes on design phases.

3. Developing

Now, it is a botton-up sequence, designing each block up to the top entity.

1.- Synthesise and test the CLK_generator.  This is an example file which can be in this problem:  a freq_div_25.vhd. Modify it conveniently to generate other similar components. Thus, organise the complete CLK_Generator using frequency dividers and T_FF to square the pulsed waveforms.  

While examining the EDA results, the RTL schematic, be aware of the number of registers (D_FF) used in the target chip and justify the value. Does it match your initial estimation?

2.- Synthesise the Datapath. For instance:

Go back to P7 and:

A.- Learn how the component Counter_mod16 works. It is necessary to comprehend this component and their many features before using it for some purpose. You have it all designed as a plan Y tutorial and you can play even with it using the simulator Proteus or the real board in the lab.

B.- Study carefully the Hour_Counter example in P7. Plan C2 on counter truncation and expansion techniques.


C.- Truncate the previous counter, because your main goal is to produce BCD_Counter_mod60.

D.- And now the Counter_MMSS and the other elements in the datapath.

Be aware of the number of registers (D_FF) used in the target chip and justify the value. Does it match your initial estimation?

3.- Synthesise the Control_unit. Assemble all the circuit  Timer_MMSS. This time, it is far better to complete the circuit and test it all together tricking the CLK_Generator to speed up simulations. 


4. Testing  (functional)

Complete the template test bench file and run the EDA tool.

Hint: in case of simulating the CLK_Generator as a component, because it is about counting tens of milions of pulses, there is a way to speed up the simulatiuon tricking the frequency dividers while keeping the number of registers used and everything else, as shown in Fig. 12. The output waveforms will be of different frequencies, but they will be synchronous and identical as in the real CLK_Generator which has to be configured in the real hardware. 

coding for simulating
 Fig. 12. Modification in the VHDL code to speed up the simulations of the CLK_Generator component. 


Print some timing diagrams and analyse that the circuit works fine in all situations.


5. Testing  (gate-level)

How fast is your circuit for a given target chip?


6. Prototyping

This is the complete project Timer_MMS solved for a NEXYS2 board as a reference for studying such complex projects.


7. Report