UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

P7

P8: Dedicated processors (datapath, control unit, CLK generator)

P9
Resources in lectures and labs: L8.1, L8.2. Project objectives

Highlighted project: MM:SS programmable timer, CLK generator

1. Specifications Planning Developing Test functional Test gate-level Report Prototype

The idea is to invent a timer circuit (Timer_MMSS) for counting down a programmable timing period up to one hour. 

Sketch
Fig 1. Front panel with main details of the Timer_MMSS application.

Circuit's symbol is shown in Fig. 2. User can program the timing period clicking  time-set up and down (TS_up, TS_down) pushbuttons.

Symbol

Fig 2. Symbol and signal naming.

The complete set of specifications and a example of timing diagram is represented in Fig. 3.

Specifications and timing diagram
Fig 3. Specifications and example timing diagram.

Our programmable timer will include the component CLK_Generator to derive all the system synchronous CLK signals from the same external 50 MHz quartz crystal oscillator.

This is a complex project where we recommend practising teamwork (1), project and time management (2) and English (4).

Organise the general architecture of the Timer_MMSS in Fig. 2 as a dedicated processor.

Target boards and programmable chips: Xilinx Digilent Nexys2, Intel Terasic DE0, DE10-Lite.

Other design tutorials and assignments.

 

Specifications 2. Planning Developing Test functional Test gate-level Report Prototype

Fig. 4 represents the general unified framework of an advanced digital system or dedicated processor. Many applications and subsystems can be created using this powerful plan C2 based on three significant component: data transmitters and receivers, A/D and D/A converters, digital filters, timers, etc. Many microcontroller peripherals are planned in this way.

Dedicated processor

Fig. 4. General architecture for a dedicated processor.

Chip 2: Datapath is in charge of performing operations processing input data or information.

Chip 1: Control unit, a FSM, is in charge of sequencing the algorithm or the flowchart.

Chip 3: CLK_Generator circuit is required to implement synchronous CLK signals derived from the same external high frequency quartz crystal oscillator.

The dedicated processor architecture adjusted to this project is represented in Fig. 5.  

Dedicated processor internal blocks
Fig 5. Dedicated processor main blocks.

Datapath. The main component in the datapath is the Counter_MMSS (modulo 3600) in BCD with outputs organised in minutes and seconds to drive 7-segment displays. The internal design of the Counter_MMSS is discussed below in Annex 1.

Datapath
Fig 6. Datapath internal architecture.

Control unit. The idea of the state diagram is sketched in Fig. 7. Its aim is to interface input buttons, generate internal control signals for managing the datapath, and generate external outputs. This block is designed following our standard FSM procedure as any other P6 application.

State diagram
Fig 7. State diagram to run the control unit FSM.

The third block is the Chip 3 CLK_generator that will supply all synchronous CLK signals for the dedicated processor. It is our standard hierarchical circuit based on plan C2. Its internal design  is discussed below in Annex 2.

This is the project location:

C:\CSD\P8\Timer_MMSS\(files)  

 

Specifications Planning 3. Developing Test functional Test gate-level Report Prototype

At this stage, the process to follow is a bottom-up sequence: (1) design each block in the architecture using components from digsys, (2) complete the top entity.

We can choose the target chip MAX10 10M50DAF484C7 so that at step 6 we can prototype the circuit in the DE10-Lite board.

Step 1.- Plan, synthesise and test the component Chip1 Counter_MMSS in Fig. 6. Its full project is reported below in Annex 1.

Step 2.- Plan, synthesise and test the component Chip3 CLK_generator in Fig. 5. Its full project is described in Annex 2.

Step 3.- Synthesise and test the complete dedicated processor Timer_MMSS in Fig. 5. Testing the components Control_unit or Datapath separately is too complicated, and at this level is better to tackle all the project. Example files: Timer_MMSS.vhd, MUX_2.vhd, Datapath.vhd, Control_unit.vhd.

RTL schematic for the Timer_MMSS
State diagram

Fig 8. RTL for the full project .The Control_Unit state diagram is coded in one-hot. 

Project summary indicates that up to 52 D_FF are used.

Technology view

Fig 9. Technology view for the full project Timer_MMSS.

While examining EDA results, project summary, RTL and technology schematics, be aware of the number of registers (D_FF) used in the target chip and justify the value. Does it match your initial estimation?

 

Specifications Planning Developing 4. Test functional Test gate-level Report Prototype

Complete the template test bench file and run the EDA tool.

testbench fixture

Fig 10. Initial testbench fixture. To follow how the machine is running the state diagram, descent the hierarchy and add internal signals to the wave diagram, such SYS_CLK and current_state.

Print some timing diagrams and analyse that the circuit works fine in all situations. Fig. 11 is an example.

Frequency dividers has to be tricked to speed up simulations, for instance, instead of dividing by 125, let it divide by 3. Remember that Start and Stop pulses must be longer that SYS_CLK period. This is an example Timer_MMSS_tb.vhd and a wave setup wave.do. 

Frequency dividers trick
Simulation results for the Timer_MMSS

Fig 11. Simulation results.

In this application, preparing testbench stimuli and running simulations is not that simple, and it is clear that for such complex real-time circuits board prototyping and laboratory experimentation is a better option. 

 

Specifications Planning Developing Test functional 5. Test gate-level Report Prototype

Optional. Gate-level and timing analyser can be used for proposing new questions and further research. For example:

- What is the time  precision of such programmable timer?

- How the value of the SYS_CLK frequency can affect timer performance? In this application we have chosen 100 kHz. What may be the difference if we select 10 MHz? 

- How to invent a programmable timer in the range of tens of nanoseconds?

 

Specifications Planning Developing Test functional Test gate-level 6. Report Prototype

By now, you know very well how document your project and what is assessed. Project report: sheets of paper, scanned figures, file listings, notes or any other resources. Follow this rubric for writing reports.

 

Specifications Planning Developing Test functional Test gate-level Report 7. Prototype

DE10-Lite board (Intel FPGA, Terasic)

Prototyping the Timer_MMSS in a DE10-lite board. Organise a Timer_MMSS_top circuit to condition buttons, LED and displays.

Switches

Fig 12. Switches and keys used as inputs. Switches generates both digital values, Pushbuttons are active-low,

OSC_CLK_in

Fig 13. 50 MHz OSC_CLK_in signal from the board's CLK subsystem, a CLK generator chip itself.
 
HEX
LED Timer

Fig 14. LEDs are active-high. 7-segment displays are active low. Each segment is connected to an FPGA pin.

Buzzer

Fig 15. Piezo buzzers are used for making beeps and alerts. We can them using square waves from 3 V to 30 V. Connect one pin to GND (either one) and the other pin to a square wave out from your digital circuit. For instance, the expansion connector GPIO9 (pin V5). We will apply the squared 1.6 KHz frequency signal named Soundwave.

We can use one of the free displays for representing the signal Alarm_LED as character "A". And we add a new output at the Control unit to monitor the internal current state of the machine in another free digit. 

Top schematic

Fig 16. Complete schematic Timer_MMSS_top.vhd

This is the Timer_MMSS_top_prj_pin.csv pin assignment file list that you can import to your Quartus Prime project. This is the final Timer_MMSS_top_prj_pin.sof to program the chip. This is the complete file list Timer_MMSS_top.zip included in this prototype experiment.

Prototype running

Fig 17. Prototype running.

  

Nexys 2 (Xilinx FPGA, Digilent)

Naturally, other similar training boards can be used to implement the prototype. For example, an additional multiplexed display system (MDS) is required for adapting the design to the 7-segment displays available in the Nexys2 board from Digilent. The design of such circuit is fully  described in the tutorial MDS because this controller can be used in many other applications. Imagine a 12-digit calculator display driven with only 19 pins  instead of 84 pins).

Symbol and application

Fig 18. Proposed symbol of the MDS. Only one common anode will be active-low at a time.

In this project we can drive the MDS from the 1.6 KHz squared signal.

This is the complete project Timer_MMSS list of files for Nexys 2. In the laboratory we can experiment measuring circuit performance.

 

7. Report

Follow this rubric for writing reports.

 

Annex 1: Counter_MMSS

The design of the Datapath Chip1 is executed and reported as a full example project tutorial at Counter_MMSS because it can be used as a module in many other industrial applications. MMSS means that this product will count in BCD modul 60 as it is necesary when chaining the counting of minutes and seconds. Range is and and down from 00:00 to 59:59.

 

Annex 2: CLK_Generator project

The design of the Chip3 is executed and reported as a full example project tutorial at CLK_Generator. This is a key circuit in our dedicated processor unified architecture. All applications will require this chip to supply synchronous clocked signals.