UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 2 problems

      - D2.6 -

-- Designing a 7-segment digit sequencer

Problems

D2.5

D2.7

1. Specifications

We want to design a simple driver to show a sequence of movement, clockwise and counter-clockwise, in a single 7-segment display. Fig. 1 represents the schematic diagram of the application. CLK signal to move segments is a 5 Hz rectangular wave. r instance 5 Hz. There is a switch to configure movement direction: CW = '1', clockwise;  CW = '0' counter-clockwise. 

Sequencer circuita)
Movement
Control signals

Fig. 1. a) Circuit schematic. b) Digit segments and position when idle. c) Sequence of switching LED segments for CW = '1' clockwise or up-counting.  

Fig. 1c shows the sequence of segment lighting when CW = '1'. When the system remains idle, the only segment lighting continuously is g.

When clicking the push-button start/stop ST_L the system runs continuously in the configured direction.

When running, if ST_L is clicked again, the system stops after completing the sequence.

 

2. Planning

 Because of the requirement that the sequence must end only when completed after detecting an ST_L falling edge, we need a 1-bit memory cell to save this event, for instance am RS_Latch. When running, the FSM will generate the sequence as if it were counting in one-hot, one LED segment at a time. Therefore, this is a plan C2 system composed of a top design (sequencer) and some components.

Some questions to kick off the project.

Infer a circuit for solving this project. Fig 2. shows an example internal design using two components. Once used (acknowledged), the ST_Flag has to be reset, thus, the FSM has to generate as well the internal signal CLR_F for the RS_Latch.

Sequencer rchitecture

Fig. 2. Sequencer circuit internal architecture.

Firstly we will design the FSM chip, secondly we can proceed with the other components.

FSM

Draw some waveforms in a timing diagram as in Fig. 3.

Timing diagram

Fig. 3. Example timing diagram when clicking STB several times.

Imagine how the FSM circuit will work. Infer how many resources the circuit may contain and try to draw a state diagram for the circuit's FSM as shown in Fig. 4. 

Diagram

Fig. 4. Idea of state diagram for this application.

Apply the FSM architecture to this problem.

Deduce how many D_FF are required when encoding FSM states using the following options and draw the state register memory:

Option #1: radix-2 (sequential)

Option #2: Gray

Option #3: Johnson

Option #4: one-hot

Draw the state register based on D_FF considering your state encoding option.

Write the truth table of CC2 and CC1 and their equivalent behavioural interpretations (plan B) using flowcharts.

Project location:

 C:\CSD\P6\sequencer\(files)

Write the FSM VHDL file.

Start a Quartus Prime synthesis project for one of the following programmable target chips:

Option #1: Cyclone IV EP4CE115F29C7

Option #2: MAX II EPM2210F324C3

Inspect and annotate the RTL and technology views. Check the number of D_FF synthesised in this application.

Sequencer

Design the RS_Latch component using gates as in L5.1 or using SD and CD in a JK_FF or T_FF disabling the synchronous inputs with CLK = J = K = '0'.

 

Prepare a VHDL testbench fixture to adapt the stimulus signals in the Fig. 5 sketch. Rely on the constant CLK_Period for setting the time scale.

Timing diagram

Fig. 5. Testbench fixture. What inputs, outputs and internal signals are to be monitored?

Run functional simulations to verify your design. Visualise as well in the wave timing diagram the internal states.

Measure the propagation time CLK to output (tCO)using gate-level simulations.

What may be a good estimation of the maximum frequency of operation? Explain your answer.

 

Optional (P8 content). Design a circuit to generate the 5 Hz square wave from a 50 MHz quartz crystal oscillator and deduce the number of D_FF that this  CLK generator will contain.

 

Optional (P8 content). Add a timer so that after 2 minutes in Idle state, the system goes to Blank state to save consumption.