UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 2 problems

      - D2.6 -

-- Designing 7-segment digit sequencer




1. Specifications

We want to design a simple driver to shown a sequence of movement, clockwise and counter-clockwise, in a single 7-segment display. Fig. 1 represents the schematic diagram of the application. The circuit components are: (1) a clock to produce a rectangular wave with a given frequency, let us take for instance 5 Hz; (2) the digital system named sequencer and (3) the 7- segment display (common cathode) with its current-limiting resistors.

UD_L = '1', clockwise;  UD_L = '0' counter-clockwise

Symbol and schematic

Fig. 1. a) Block diagram of the circuit. b) Digit segments and position when idle. c) Sequence of switching LED segments for UD_L ='1' (clockwise / up counting). 

The system has to work as specified in Fig. 1c, depending on the logic levels of the synchronous input signals: UD_L (Up, active high / Down, active low) and ST (start/stop). A start pulse (ST) activates the sequence of LED lighting that never ends until another pulse ST is applied and the sequence reached the last state. Because of the requirement that the sequence must end (for example when going UP reaching the state Blank) before stopping (going Idle) if another ST pulse is detected, the design must include a 1-bit memory cell such as an RS_Latch or an RS_FF and the FSM that generate the sequence and controls the system. Therefore, this will be a plan C2 system composed of a top design (sequencer) and some components.

Some questions to kick off the project and organise it in four phases. Apply the FSM architecture to this problem.

a) Infer a circuit for solving this project.


Fig. 2.

b) Particularise the internal FSM component architecture to this problem, naming and connecting all the inputs and outputs.

c) Infer and draw the circuit's state diagram. Annotate all the state transitions and outputs.


Fig. 3. Idea of state diagram for this application.

d) Sketch a timing diagram showing the main operations. In addition to the ports, include as well internal signals like STB in the discussion.

e) Draw the state register if coding the machine in binary sequential. How many D_FF of memory are used in this problem?

f) Write the CC2 truth table to obtain the outputs of the circuit and its flowchart.

g) Design the CC1 truth table to obtain the next state to go and its flowchart.

h) Write the VHDL files (this is a plan C2 design) and run the EDA project to synthesise the circuit and obtain results. Inspect the RTL and verify that it looks like your schematic. Check the number of D_FF, print and comment the schematics.

i) Write a VHDL test bench and run the EDA simulation tool to verify your design.

j) The target chip is an Inel MAX II. What may be a good estimation of the maximum frequency of operation? Explain your answer.

k) Design a circuit to produce the 5 Hz square wave from a 50 MHz quartz crystal oscillator and deduce the number of D_FF that this  CLK generator will contain.