UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

 

Bicycle flashing lamp with a single push-button

P6

Basics on synchronous FSM

1. Define requirements

Let us design a flashing lamp like the one represented in Fig.1 similar to the torches used in bikes. A single button to switch modes of operation: clicking once the lamp turns ON, clicking again it blinks with a 5 Hz frequency, and clicking for the third time it turns OFF. Let us use a 1 KHz CLK signal to synchronise the application.

This is the FSM design approach targeting a programmable device like a CPLD or a FPGA for prototyping.

torche

Fig. 1. Example of a commercial LED flashing torch for a bicycle. 

 

Circuit symbol and power-on reset circuit that makes optional an external CD button.

A CLK_generator will be required to obtain the CLK_1kHz_SQ and CLK_5Hz_SQ signals from an external high frequency oscillator. 

 
Symbol
Power-on Reset concept

A typical sequence of signals is presented in Fig. 2. We can also imagine internal states as long button clicks are detected.

Timing diagram

Fig. 2. Example timing diagram imagining internal states.

 

2. Planning

We aim to design the circuit Lamp_Control FSM in Fig. 3 using a FSM strategy. The circuit can easily be expanded with more modes of operation connecting other signals to the output multiplexer.


Flashing_lamp 

Fig. 3. The proposed circuit based on a synchronous FSM.

Chip2 MUX_4 selects ON ('1'), OFF ('0') or intermittency (5 Hz). New light signals can be easily added in other channels. 

Let us infer the state diagram so that the system has enough internal memory to remember the three consecutive clicks from the the same push-button ON_B.  As you see in Fig 4, up to 6 states are required.

State diagram

Fig. 4. State diagram for this application. 

 The project will contain 3 VHDL files, the top entity Flashing_Lamp, and the two internal components: MUX4 and Lamp_control.

 This is the proposed FSM with all the connections and the truth tables of the CC1 and CC2 combinational circuits, so that they can be later easily translated to VHDL along with the state register. Note how before translating a truth table to VHDL, the flow chart (or Algorithmic State Machine chart, ASM) is required.

 How many DFF registers will be required in this project if coding the internal states in binary (sequential) or in one-hot?

 How can we deduce a frequency divider to obtain the squared 5 Hz waveform from the input 1 kHz CLK? It is assumed that two squared signals (CLK_1kHz_SQ, CLK_5kHz_SQ) are generated externally by means of other circuits (CLK_generator).

 

3. Develop the project and implement the hardware

VHDL codes: top entity Flashing_Lamp.vhd, MUX4.vhd from a previous project in P2, and Lamp_Control.vhd that contains the FSM.

Project name is Flashing_Lamp_prj and the project location is: 

 C:/CSD/P6/Flashing_Lamp/(files)

Let's see if the EDA tool synthesiser interprets correctly the high-level (behavioural) FSM descriptions producing the RTL picture in Fig. 5.

RTL_1

Fig. 5. The RTL schematic. 

Check the binary code in which the FSM is encoded and the number of 1-bit memory registers used (DFF). Here in Fig 5. there is a detailed RTL view of the FSM that contain all the registers. Using a binary "sequential" encoding, 3 DFF can hold up to 8 states.  

RTL_2
 

 Fig. 5. Number of registers used in the synthesis of the circuit.

This is the report text file where the FSM encoding can be seen:

Encoding states

 

Alternatively, it is possible to change the FSM encoding parameter to for instance "one-hot"  (6 registers).

Encoding in one-hot

 

4. Test & verify

This is a sample test bench file Flashing_Lamp_tb.vhd

1) Functional simulation. Run the EDA VHDL tool and demonstrate how the circuit works adding comments to the printed sheet of paper containing the waveforms. Naturally, CLK of very different frequencies cannot be seen at the same time scale. Thus, to see how the system sample the values of the ON_B at the rising edge of the CLK, you have to zoom as in Fig. 7.

Waveforms simulation
 

Fig. 6. Example of a timing diagram to show how the circuit works.


Waveform viewer
 

Fig. 7. Zoom at the system CLK scale to observe the synchronicity.

5. Report

Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources

 

6. Prototyping

Once the circuit works in the simulator, the idea is to continue the project development in the laboratory to download the project's configuration file into a given CPLD or FPGA. In our lab, there are several training boards, for instance the Digilent Coolrunner which is populated with a CPLD. Thus, it is time to verify how the circuit works in real and use the instrumentation to make measurements. 

In Fig. 8 are the PLD pin assignment used in this application, which, as described in the board's datasheet, are connected to push-buttons and LED's.

pin assigment

Fig. 8. The pin assignment file (ucf) easily produced using the spreadsheet in ISE.

 

pin assigment

Fig. 9. Detail of the board datasheet. Three LED are used for debugging purposes to show the current_state vector value.

The CLK_generator is required to obtain CLK_1kHz_SQ and CLK_5Hz_SQ from the board main quartz oscillator of 8 MHz, completing the internal schematic of the Flashing_Lamp.

This is the list of all the source files to complete this project and in Fig 10 is a picture of the board running.

demo

Fig. 10. The prototyping board populated with a Xilinx Coolrunner CPLD.

This is a video showing the sequence of operations triggered when pressing the ON_B.

 

The same project can be easily adapted to other PLD boards from different vendors considering the board's hardware and oscillator frequency. For instance, this Nexys 2 board has a quartz oscillator of 50 MHz.

This is the flashing lamp using a DE2-115 board from Intel and Cyclone IV FPGA