UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 2 problems

      - A2.4 -

-- Analysis of an asynchronous circuit




1. Specifications

The circuit represented in Fig. 1 is composed of JK_FF and logic gates. Let us deduce how it works and what may be its application. This is an example of an asynchronous circuit that can serve to demonstrate how complicated and unreliable is asynchronous design compared to synchronous canonical design based on FSM that is presented in the next P6.


Fig 1. Circuit_Async2 to be analysed using up to three methods. Draw this circuit in you own sheet of paper.

Phase 1: analyse the JK_FF memory cell component.

a) Analyse the behaviour of the JK_FF in Fig. 2 and represent the output Q in a timing diagram like the one represented in Fig.3.


Fig 2.  JK_FF symbol, function table and state diagram.

Indicate always J and K sampled values using dots.



Fig 3. Example input waveforms to be used as stimulus for calculating the output Q. 

b) Chip2 is working as T_FF. Analyse the behaviour of the T_FF.


Phase 2: circuit analysis. Three methods proposed.

c) Method 1: Handwritten pen-and-paper analysis and discussion. Deduce the output Q(2..0) of the circuit represented in Fig. 1. The procedure is presented in P5 highlighted project.

This is a video rec. that explains the problem planning and solutions, the last part of which shows how to deduce the timing diagram in paper.


Fig 4. Waveforms.

This method is developed in paper and results are verified by comparing with other methods.

Discuss how many states the system is capable of memoring.

Discuss what may be the function or application of the circuit. What is the circuit's main problem, so that it must be rejected for precision applications?  


d) Method 2: using Proteus.

Capture Fig. 1 in Proteus and run simulations. For instance copy and adapt a similar structure such Proteus circuit based on CMOS classic chips. When picking parts from the library to mount your circuit, do this initialisation from Proteus top menu:

 --> Tool --> Global Annotator --> Total.

Project location:



e) Method 3: using VHDL synthesis and simulation tools (plan C2 circuit).

Get the component JK_FF model and translate to VHDL the circuit fully annotated in Fig. 5.

Synthesise the project and print the RTL view. Be aware that the "number of registers" in the project's summary spreadsheet must be "3". Use a VHDL test bench to demonstrate that the timing diagram looks like that obtained in Proteus or in the analysis above.



Fig 5. Example of the fully annotated circuit to be translated to VHDL. It can be named Circuit_Async2.vhd


Optional: Canonical circuit based on FSM.

f) Design an FSM that generates the same output Q(2..0). It will be a better replacement of the asynchronous circuit in Fig. 1. Why?