UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 2 problems

      - D2.7 -

-- Dumbwaiter or simple lift

Problems

D2.6

D2.8

1. Specifications

Our company has to design the control system for a simple dumbwaiter (a small freight elevator used to transport food, wine, and other items between stories of a residential building) ordered by our client. It will transport loads between a 2-storeys kitchen. Fig. 1 shows a photograph of an installed commercial dumbwaiter and a detail of the motor and the control system installed under the car.

Dumbwaiter

Fig. 1. Photograph of a commercial dumbwaiter.

Some questions to kick off the project and organise it in four sections. Apply the FSM architecture to this problem.

a) Produce a sketch of the dumbwaiter system that includes up and down buttons for both levels, location of the floor sensors, green and red LED�€™s, and outputs for driving the stepper motor. See Fig. 2.

- U1, D1, U0, D0: Buttons for calling the car.

- LS1, LS0: Limit switches to detect the presence/absence of the car at each storey.

- RST is similar to CD: if pressed or after power on, this signal takes the car to the initial state with the car stopped at storey 0.

- GL1, RL1, GL0, RL0: LEDs for indicating operation: green LED is ON when the car is stopped in the corresponding storey, red LED is ON when the car is moving between storeys.

- INH. Inhibit signal to prevent motor movement.

- UD_L: Up movement when high and down when low if INH is not activated.

Sketch

Fig. 2. Sketch of the 2 storeys dumbwaiter indicating sensors, pushbuttons and output functions to drive the stepper motor and the LED.

b) Draw the symbol of the entity to be designed.

Symbol

Fig. 3. Symbol.

c) Adapt the FSM architecture to this problem, naming and connecting all signals and inputs and outputs.

d) Infer and draw the circuit's state diagram. Annotate all the state transitions and outputs.

Diagram

Fig. 4. State diagram.

e) Sketch a timing diagram showing the main operations.

f) Draw the state register if coding the machine in binary sequential. How many D_FF of memory are used in this problem?

g) Write the CC2 truth table to obtain the outputs of the circuit and its flowchart.

h) Design the CC1 truth table to obtain the next state to go and its flowchart.

i) Write the VHDL file and start an EDA project to synthesise the circuit and obtain results. Inspect the RTL and verify that it looks like your schematic. Check the number of D_FF, print and comment the schematics.

j) Write a VHDL test bench and run the EDA simulation tool to verify your design.

k) CLK frequency will be adapted to drive the stepper motor. Let us imagine that it is D2.2. Let us rotate the motor at three revolutions per second. Design the  CLK generator circuit from a 50 MHz quartz crystal oscillator. Deduce the number of D_FF that it will contain.