﻿ Digital Circuits and Systems - Circuits i Sistemes Digitals (CSD) - EETAC - UPC
 Bachelor's Degree in Telecommunications Systems and in Network Engineering
 Laboratory Laboratory 1_2: analysis of simple circuit using VHDL EDA tools [P1] - analysis  method IV: Circuit synthesis. RTL view. [9/3]
 Individual post lab assignment PLA1_2 to be discussed next Lab2. Study and execute this lab tutorial before attempting to solve the post lab assignment.

1.4.4. Analysis method IV using VHDL synthesis and simulation EDA tools

Before advancing towards P2 on the design of standard combinational circuits using VHDL tools, let us discover how to solve the last P1 analysis method IV  using VHDL language and electronic design automation  to synthesise and simulate a circuit with the aim of deducing its truth table.

NOTE: Students must install software EDA tools in personal computers.

1. Specifications of what do we have to do

Find the truth table of Circuit_W  represented in Fig. 1 using VHDL synthesis and simulation tools.

 Fig. 1. Symbol and internal architecture of Circuit_W to be analysed.

Draw an example of timing diagram showing how to drive inputs, so that the truth table (circuit output) can be deduced using a VHDL testbench in ModelSim tool.

 Fig. 2. Example timing diagram showing some input combinations.

2. Planning the analysis project

The plan requires, as in method II (WolframAlpha) or method III (algebra), obtaining the circuit's equation that this time will be translated to VHDL.

- Find a similar file to copy and adapt. For example from this on Quartus Prime installation. Rename and save it as Circuit_W.vhd at this project location:

C:\CSD\P1\Circuit_W\VHDL\(files)

- Write the circuit equation in VHDL.

- The tool for synthesising the equation will be Intel Quartus Prime. The tool for simulating the circuit will be ModelSim Intel Starter Edition. Select an Intel target chip, for example, the CPLD MAX II EPM2210F324C3 chip.

 Fig. 3. Planning the solution.

- Start a Quartus Prime project and synthesise the circuit. Examine the RTL and the technology schematics.

- Draw a VHDL testbench fixture for the chip under test.

- Generate an skeleton testbench in Quartus Prime. Move it to the project folder and rename it as Circuit_W_tb.vhd

- Complete the stimulus process with some input activity, for example with some signals from Fig. 2.

- Run the simulation and examine wave analyser results.

- Complete all the combinations  and write down the circuits truth table.

- Check the truth table comparing results from other methods.

3. Developing (finding the problem's solution)

Start obtaining the equivalent circuit equation using paper, as in Fig. 4.

 Fig. 4. Analysis gate by gate in order to find the equivalent algebraic equation.

NOTE: Use in CSD the enriched text editor, a very convenient free tool for writing VHDL and C files. Another free enriched editor is Scriptum from the company HDL Works.

Translate the equation  into a VHDL source file. This is a VHDL source file example Circuit_W.vhd.

Start a new synthesis project targeting a commercial programmable logic device (PLD) or field programmable gate array (FPGA) chip. Here you have several devices available in our labs for experimentation. For instance, let us select an Intel CPLD MAX II EPM2210F324C3 chip.

• Project name: Circuit_W_prj

• Top entity: Circuit_W

Run the synthesis process and examine RTL and technology views.

Print the circuits using snipping tool (or any other similar tool like Snagit from TechSmith). Discuss differences between the two schematics. How many resources are used (logic cells or macrocells)?

 Fig. 5. RTL example picture.

Finally, as shown in Fig. 6, the circuit is synthesised in a single cell using SoP equation minimised by Quartus Prime.

 Fig. 6. Technology view when targeting a MAXI chip.

 Fig. 7. Example of logic cell to implement functions. MAX II EPM2210F324C3 contains 2210 logic elements.

 Laboratory Laboratory 1_2: Analysis of simple circuit using VHDL EDA tools  [P1 - Section A] method IV: Circuit simulation. VHDL testbench [9/3]

Now that we have the circuit synthesised by Quartus Prime in a MAXII device, it must be simulated to obtain its truth table.

Generate a testbench template in Quartus Prime. Fig. 8 represents the idea behind a VHDL testbench. Rename the file from Circuit_W.vht to Circuit_W_tb.vhd and move it to the project location folder.

 Fig. 8. VHDL testbench concept.

Using the example timing diagram in Fig. 2, translate into VHDL the stimulus signals into a process and set the constant Min_Pulse. This is a VHDL testbench example Circuit_W_tb.vhd from which you can copy only the stimulus process and Min_Pulse constant.

Start a project in ModelSim Intel (or in Xilinx ISim or in Active-HDL).

 Note: remember to change preferred colours in ModelSim when using it for the first time (white background must be used when printing).

Project location: C:\CSD\P1\Circuit_W\VHDL\   (The same location as above for synthesis)

Project name: Circuit_W_functional_sim

Project library: work_functional

Run the simulation process and extract the truth table from the inspection of the logic analyser display (wave window) using time cursors, as represented in Fig. 9.

 Fig. 9. Example waveforms from ModelSim.

 Fig. 10. Circuit_W truth table and its canonical equations.

4. Testing analysis results

Verification of the truth table. Compare your truth table with results from other methods. For instance, from method I or method II in Lab1_1 or method III in . In this way, this section has to say something as simple as

"My Circuit_W generates the same truth table using method IV and method III".

5. Reporting

• Follow this for writing reports.

6. Prototyping Circuit_W

These are basic ideas consisting of drawing a top schematic to adapt the project to the specific board hardware. Because it is a hierarchical multiple-file design, any circuit based on can be copied and adapted to be the top entity.

DE10-Lite board. This page MAX10 DE10 Lite contains information and the used manual.

Fig 11. shows the schematic to adapt the Circuit_W to the FPGA MAX10 populating the DE10-Lite board. All our prototype adaptations will be named in the same way: we will identify the component under design "Circuit_W" and add "_top" suffix.

Prototype location:

C:\CSD\P1\Circuit_W\DE10_Lite\(files)

 Fig. 11. Schematic consisting of a top entity with the component and the glue logic to adapt inputs and outputs to the board's hardware. Studying the schematics we see that the switches are connected through a series 120 W resistor to the FPGA pins for protections purposes (pins are also avaialbe at expansion connectors).          The two keys, KEY0 and KEY1, are buffered using a SN74LVC2G17 chip and they are active-low including as well an RC debouncing filter.

Using pin planner tool at Quartus Prime navigator we connect signals to FPGA pins. We can export the asignment to a file to keep it save.

 Fig. 12. Pin plannet tool allows assigning circuit signals to FPGA pins.

This zipped file Circuit_W contains all the required files for implementing project. As shown in Fig. 13 the programmer tool is used to download the configuration file to the FPGA target chip.

 Fig. 13. Programmer and circuit running for final checking and verification.

Note: This is another complete tutorial example on introducing and prototyping on the .

MAXII Micro kit. This is the board MAXII Micro kit board.

Fig 14 shows the training board populated with a MAX II chip. Expansion connectors in areas A and B  can be soldered so that many more FPGA I/O pins are avaialble for prototyping designs.

Prototype location:

C:\CSD\P1\Circuit_W\MAXII_Micro_kit\(files)

 Fig. 14. Lab training board populated with MAX II EPM2210F324C3 for experimentation.

As shown in the top schematic in Fig. 15, for this simple project only the buttons and a single LED will be used.

 Fig. 15. Schematic consisting of a top entity with the component and the glue logic to adapt inputs and outputs to the board's hardware.

The zipped project Circuit_W containing all the required files to complete this experiment.