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Bachelor's Degree in Telecommunications Systems and in Network Engineering |
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Laboratory |
Laboratory 1.2: analysis of simple circuits based on logic gates Method III on VHDL: synthesis + simulation + FPGA prototype. [P1] for practising |
[23 Sept] |
This is the individual post lab assignmentPLA1. |
1.4.3. Analysis method III using VHDL synthesis and simulation EDA tools
Before advancing towards P2 on the design of standard combinational circuits using VHDL tools, let us discover how to solve the last P1 analysis method III rec. using hardware description language VHDL and electronic design automation EDA tools to synthesise and simulate a circuit with the aim of deducing its truth table. Additionally, we also have the option to configure the FPGA prototype board DE10-Lite.
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Project tutorial: Analysis of the Circuit_W |
| Chapter 1 | Chapter 2 |
| PROTEUS VSM(9.0 SP6) minilog.exe Notepad++ | |
| VHDL | |
| Digilent WaveForms Terasic DE10-Lite USB Blaster driver | |
| Home Term 25/26-Q1 Contact Products Electronic devices and companies Software Books Magazines Instruments DEE Library EETAC DEEL |
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| Web activa des de 09/2001, @ F. J. Robert, Web editat amb Microsoft Expression Web 4. El contingut és un complement als materials d'estudi del curs Circuits i Sistemes Digitals disponibles al campus digital Atenea. Llicència:Reconeixement 4.0 Internacional de Creative Commons |