Digital Circuits and Systems - Circuits i Sistemes Digitals (CSD) - EETAC

P10: FSM in C language (software FSM), external interrupts

P11

Resources in lectures and labs:

L10.1, Lab10, L10.2

Project

objectives

Highlighted project: 4-bit serial transmitter (design phase #1)

1. Specifications

Let us design a simplified 2-wire (Serial_out - GND) asynchronous data transmitter based on a μC for sending a nibble (4-bits) of data to another computer or device. The symbol is represented in Fig. 1. Asynchronous transmissions based on Shift_Reg_4bits devices were studied in the USART tutorial (rec. part 1).

The target chip is a PIC18F46K22. We will program the application in C language using our FSM style. The format for the serial output once the start-transmission (ST) rising edge is detected by means of an interrupt is: Start bit ('0'); Data_in(0), Data_in(1), Data_in(2), Data_in(3); Stop bit ('1'). And while transmitting the stop bit, the end-of-transmission EoT pulse is generated to indicate that the transmitter has ended the process. The output Serial_out is held high when idle (marking).

Fig 1. Symbol for the 4-bit serial transmitter.

Fig. 2 shows an example of timing diagram to start transmitting data when the ST pulse is detected.

Fig 2. Example of a section of a timing diagram where it can be seen how the data is read and right shifted in a single wire.

Serial transmission (TX) and reception (RX) is used in every electronic equipment. For instance, Fig. 3 shows two examples:(a) the PC computer COM serial port and its options to choose transmission parameter; (b) the communication between ECU (electronic control units) in modern autonomous vehicles.

a)

b) autonomous vehicle

Fig 3. a) Example of the PC COM port configuration parameters for enabling asynchronous communication. This standard port can be emulated by Bluetooth or USB adapters. b) Autonomous vehicles generate huge amounts of data to be transmitted from and to high-speed digital subsystems. Reference: Keysight white paper: "High-Speed Digital Design Success Demands A Modern Workflow" (pdf).

Logically, we can enhance our simple transmitter in successive design steps to implement for instance all the options available in the conventional COM PC port.

Furthermore, we can design the receiver that complements this asynchronous transmitter.

The idea that we have in mind in this Chapter 3 on designing software FSM is very well explained in this white paper from the microcomputers company ARM.

A) Planning hardware

The electronic circuit sketch is shown in Fig. 4. Some μC port pins are selected to be inputs and outputs, external interrupt INT1 is used to detect ST active edge event (falling or rising signal transition) to start sequencing the transmission. External interrupt INT0 will detect an active edge from the external CLK to be able to serialise one bit per period. The key concept in this application is detecting signal edges using interrupts. CLK interrupt can be both, enabled all time or instead, better only after start transmission edge is detected.

Fig. 4. Hardware used in this application. The 2-wire serial output cable can be simulated using a resistor R0 = 10 kW. The PIC18F46K22 has three port pins (RB0, RB1 and RB2) able to generate external interrupts (INT0, INT1 and INT2) when detecting signal edges (the active rising or falling transition is configurable).

B) Planning software

The general idea is represented in Fig. 5 (rec. part 2). The concepts of CC1 and CC2 combinational circuits inherited from Chapter 2 have the same meaning, we will implement this logic using software routines.

Fig. 5. Software organisation used in this application. Because current_state is saved in a memory position and updated every main loop cycle, there is no need of next_state variable as it was the case in Chapter 2.

And even a clearer flowchart reorientation of the software organisation in Fig.6 below.


	Fig. 6. General interrupt-driven FSM-style program organisation (Visio).

Therefore, it is possible to think in terms of a kind of hardware/software diagram as shown in Fig. 7. The idea of implementing a "FSM in software": state and output logic connected to RAM variables and additional functions related to hardware (drivers) to read and write external pins. The diagram also includes the interrupt logic hardware capable of triggering the jump from the main program execution to the interrupt service routine (ISR).

Fig. 7. This diagram connects in a convenient way the hardware section and the software functions for better understanding the idea of programming FSM.

Draw the state diagram, so that the sequence represented in Fig. 2 can be generated after having detected an ST edge.

Fig. 8. Proposed state diagram. Be aware that all the signals represented are RAM memory variables, for instance, CLK pin is now the var_CLK_flag. When the ST button active rising edge is detected, the FSM needs six CLK periods to complete the transmission and to go back to idle state to wait for the next ST pulse.

In Fig. 9 there is the representation of the RAM memory required in this project. At our introductory level, memory positions are not optimised in any way. Our main goal is clarity and simplicity, and thus, we like to save each signal in a different memory position zeroing all the unused bits.

Another convention to make it simple is to code FSM states in a RAM byte variable named var_current_state. Let us use ASCII capital letters to facilitate interactive debugging using the watch window. Remember that this state encoding was proposed in Chapter 2 as an option to choose between several codes: sequential, Johnson, one-hot, Gray, etc.

Fig. 9. We will use six bytes of RAM to store the variables.

Draw the main ideas of init_system(). Configure input and output pins. Consider as well interrupts configuration.

Fig. 10. Example of TRIS configuration.

Draw the flowchart of read_inputs(). Basic function to poll input voltages as in L9.3.

Fig. 11. Reading inputs ideas.

Draw the flowchart of write_outputs(). Basic function to write pin voltages as in L9.4.

Fig. 12. Example on how to write output pins.

Infer how to organise the interrupt service routine ISR() to handle edge detections. Any time that an interrupt occurs the main program execution stops, all the registers, flags and environment is saved at the stack memory, and the the program counter jumps to the interrupt vector where is written the ISR() code. When returning from interrupt restores the environment is restored and the program counter continues executing main loop instructions.

Fig. 13. Ideas on how to organise the ISR.

And now, it is necessary to discuss how to transfer all the state transitions into a truth table. Draw state_logic() truth table and follow interpreting it as in plan B, in a behavioural way.

Fig. 14. Truth table for state_logic() function and its flow chart interpretation. Now it is straightforward to identify C statements.

Draw output_logic() truth table. Finally, what is left to finish this project planning is the same idea but for the outputs: how to translate all the outputs in parenthesis in the state diagram into a truth able and its equivalent flowchart? This ideas are presented in Fig. 15. A Moore FSM makes it simpler than a Mealy FSM: all the outputs are perfectly defined for each state.


	Fig. 15. Truth table for output_logic() function and its behavioural interpretation flowchart.

Organise a MPLABX - XC8 IDE project targeting a PIC18F46K22 at location:

C:\CSD\P10\Serial_transmitter\(files)

3. Dev. & 4. test

A) Developing hardware

Electronic circuit and C source code. Running simulations and debugging (rec. part 3).

This is a file Serial_transmitter.pdsprj containing the circuit represented in Fig. 16. Be aware that ST and CLK inputs must be connected to external interrupts like INT1 (RB1) and INT0 (RB0).

Fig. 15. The proposed circuit running the final executable "*.cof" to be able to debug errors and step by step mode.

B) Developing software

Our planning ideas in previous section are translated to this C source file: Serial_transmitter.c. Add the config.h header to your project.

Run the microcontroller's IDE to develop and compile the C code to obtain executable files.

C) Step-by-step testing

Instrumentation can be used to display transmitted waveforms. You may like to replace the ST button by a pulse generator (for instance 0V-5V, T = 1.5 s, pulse duration = 20 ms).

Remember that development and testing must be carried out step by step, one feature at a time.

Fig. 16. Waveforms captured in Proteus showing the transmission of the four bytes once the start bit is low. NOTE: Do not print these pictures with black background. Configure and change colours to save ink when printing pictures for your reports.

- Check that the machine is always under control running through the enumerated states (watch window --> var_current_state).

- Check the duration of a transmitted bit using breakpoints.

- Check that var_ST_flag has the right values when start transmission button is pressed.

- Count the number of times the CLK interrupt is enabled.

- Calculate how fast is the execution of the main loop.

- How long does it take to execute the ISR()?

5. Prototype

Example 1: Board CSD_PICstick . Target microcontroller: PIC18F46K22. Tools: MPLAB X + XC8 + Proteus + VB8012 compact instrumentation.

A complementary project is the design of the serial receiver USART.

Example 2 optional: Board Picdem2+. Target microcontroller: PIC18F4520. Tools: MPLAB X + XC8 + Proteus

Fig. 14. PICDEM2+ board to be used with a PIC18F4520 chip. Expansion connectors or prototyping area can be used to connect switches and LED.

Example 3 optional: Board Explorer 8. Target microcontroller: PIC18F4520. Tools: MPLAB X + XC8 + Proteus

Fig. 15. Explorer 8 board to be used PIC18F4520 chip. The same code as in the previous example.

Example 4 optional, beyond the CSD learning objectives. Board Explorer 8. Target microcontroller: PIC18F46K22. Tools: MPLAB X + XC8 + MCC + Proteus. Project: Interrupt

To take full advantage of this board the programming environment requires MCC (MPLAB Code Configurator) application embedded in MPLAB X. The chip must also be upgraded for instance to PIC18F46K22, which is also available in Proteus.

This is an introductory project Interrupt.pdsprj to guide you on the use of MCC to specify hardware and peripherals. It is the same project presented in P9 where the push-button S1 generates INT0 interrupts to update Var_SW_S1. The application program Interrupt.zip is organised in multiple c files. Unzip and copy the full directory at location:

C:\CSD\P10\Interrupt\(files)

Interrupt seed project to learn on interrupts and EXPLORER 8

Fig. 16. This application can be used as a seed project to copy and adapt, no need to start from scratch. The full tutorial application that exemplifies several features of the hardware in Explorer 8 is available from Microchip product page.

6. Report

Follow this rubric for writing reports.

Home Term 24/25-Q2 Contact Products Electronic devices and companies Software Books Magazines Instruments DEE Library EETAC DEEL
Web activa des de 09/2001, @ F. J. Robert, Web editat amb Microsoft Expression Web 4. El contingut és un complement als materials d'estudi del curs Circuits i Sistemes Digitals disponibles al campus digital Atenea. Llicència:Reconeixement 4.0 Internacional de Creative Commons