UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL


P10: FSM in C language, external interrupts


Resources in lectures and labs: L10, Lab10 Project objectives

Highlighted project: 4-bit serial transmitter (phase #1)

1. Specifications

Let us design a simple 2-wire asynchronous data transmitter based on a µC for sending a nibble (4-bits) of data to another computer. It is basically the adaptation of Shift_Reg_4bits as studied in P7 controlled by a push-button ( rec. part 1).

Target chip is PIC18F4520.

We use the FSM style of programming in C language. The format for the serial output once the start-transmission (ST) rising edge is detected by means of an interrupt is: Start bit ('0'), Data_in (0), Data_in (1), Data_in (2), Data_in (3); and then the end-of-transmission EoT pulse is generated to indicate that the transmitter has ended the process. Serial_out is held high when idle.   


Fig 1. Symbol for the 4-bit serial transmitter.

Fig. 2 shows an example of timing diagram to transmit data when the ST pulse is detected.


Fig 2. Example of a section of a timing diagram where it can be seen how the data is read and right shifted in a single wire.


Other similar projects:

Counter_BCD_1digit plan X: current_state is an state enumeration

Counter_mod1572 plan Y: current_state is a variable type char, int, etc. that can contain any value

Chip_74HCT4017 plan X: 10-bit one-hot counter with internal  5-bit Johnson architecture)

Johnson_sequencer_mod12 with start/stop feature and using two external interrupt sources (CLK, ST/SP)


2. Planning

Hardware circuit and software code (rec. part 2).

Planning the hardware circuit. Represented in Fig. 3. Some pins must be selected to be inputs and outputs, and in this case, external interrupt INT1 is used to detect ST active edge event (falling or rising signal transition) to start sequencing the transmission. External interrupt INT0 will detect an active edge from the external CLK to be able to serialise one bit per period.

The key concept of interrupt.

electronic circuit Fig. 3. Hardware used in this application. The idea is to connect the CLK signal to an external interrupt pin (INT0 or INT1).

Indeed, in this application both external interrupts are required: CLK and ST.

The number of external interrupts available depend on the microcontroller chip.

Planning the software. The general idea is represented in Fig. 4. The concepts of CC1 and CC2 combinational circuits inherited from Chapter 2 are the same, however this time, we will implement this logic using a software routine.

  Fig. 4.  Software organisation used in this application. Because current_state is saved in a memory position and updated every main loop cycle, there is no need of next_state variable as it was the case in Chapter 2.

And even a clearer flowchart reprentation of the software organization in Fig.5 below.

  Fig. 5.  General interrupt-driven FSM-style program organisation (Visio).

Therefore, it is also possible to think in terms of the hardware/software diagram as shown in Fig. 6. The idea of implementing a "FSM in software" with some functions related to hardware (drivers) and the interna output and state logic software functions that process RAM variables. 

Hardware-software diagram
Fig. 6. This diagram connects in a convenient way the hardware section and the software functions for better understanting the idea of programming FSM. 

Draw the state diagram, so that the sequence presented in Fig. 2 can be generated after having detected an ST edge.

State diagram 
  Fig. 7. Proposed state diagram. Be aware that all the signals represented are memory variables, for instance, CLK is var_CLK_flag. When the ST button active rising edge is detected, the FSM needs six CLK periods to complete the transmission and to go again to Idel state to wait for the next ST pulse. 

In Fig. 8 there is the representation of the RAM memory required in this project.

RAM Fig. 8.  We will use six bytes of RAM to store the variables.

At this introductory level, memory positions are not optimised in any way. Our main goal is clarity, and thus, we like to save each signal in a different memory position zeroing all the unused bits.

Another convention to make it simple is to code FSM states in the variable current_state  using ASCII capital letters. This will simplify the watching of this important variable while debugging.

Draw the main ideas of init_system(). Configure input and output pins. Consider as well interrupts configuration.

Fig. 9. Example of TRIS configuration

Draw the flowchart of read_inputs(). Basic function to poll input voltages as in P9. 

Draw the flowchart of write_outputs(). Basic function to write pin voltages as in P9. 

Infer how to organise the interrupt service routine ISR() to handle edge detections.

And now, it is necessary to discuss how to transfer all the state transitions into a truth table.

Draw state_logic() truth table

  Fig. 10. Truth table for state_logic() function.

Translate it into a behavioural flowchart.

  Fig. 11. Tranlating state_logic() truth table into a behavioural flowchart so that C statements can be easily imagined. 


Finally, what is left to finish this project planning is the same idea but for the outputs, how to translate all the outputs in parenthesis into a truth able and the equivalent flowchart?

 Draw output_logic() truth table.

output logic
  Fig. 12. Truth table for output_logic() function.

Translate it into a behavioural flowchart.

output logic flowchart
  Fig. 13. Tranlating output_logic() truth table into a behavioural flowchart so that C statements can be easily imagined.  A Moore FSM makes it simple than a Mealy FSM, all the outputs are perfectly defined for each state.


Organise a MPLABX - XC8 IDE project targetting a PIC18F4520 at location:



3. Development

Electronic circuit and C source code. Running simulations and debugging ( rec. part 3).

Hardware. This is a file Serial_transmitter.pdsprj containing the circuit represented in Fig. 14. Be aware that ST and CLK imputs must be connected to external interrupts like RB1/INT1 and RB0/INT0.

Fig. 14. The proposed circuit running the final executable "*.cof" to be able to debug errors and step by step mode.


Software. The planning ideas in the previous section are translated to a C source file such as Serial_transmitter.c


4. Testing 

These are the project files where the Serial_transmitter project run in Proteus environment. Instrumentation can be used to display transmitted waveforms. You may like to replace the ST button by a pulse generator (for instance 0V-5V, T = 1 s, pulse duration = 20 ms).

Remember that development and testing must be carried out step by step, one feature at a time.

waves and circuit
Waves Fig. 15. Waveforms captured in Proteus showing the transmission of the four bytes once the start bit is low. 


- Check that the machine is always under control running throgh the enumerated states (watch window --> current_state).

- Check  the duration of a transmitted bit using breakpoints.

- Check that var_ST_flag has the right values when start transmission button is pressed.

- Calculate how fast is the main loop.


5. Report



6. Prototyping

Download your application configuration file (*.hex) to a training board an verify that it works as expected and in the same way it did in the simulator.



Other similar projects

- Invent the dual circuit 4-bit serial receiver and simulate both subsystems in Proteus.

- Tutorial example on the use of the Port B and external INT interrupts. Class discussion (1), (2). This is the adaptation when using this demonstration board. [Replace PIC16F877 by PIC18F4520)]

- A good example to see how the interrupt mechanism works is for instance: modify the 1-digit BCD adder so that the truth table is calculated only when an EXEC pushbutton is pressed. Hardware flag: INT0F, software variable: var_EXEC_flag.