Digital Circuits and Systems - Circuits i Sistemes Digitals (CSD) - EETAC


Chapter 1 problems	- D1.4 -	Designing circuits using plan A and plan B	Problems	D1.3	D1.5

1. Specifications

Design the combinational Circuit_VT shown in Fig. 1.

1. Plan A structural approach as represented in Fig. 2 based on logic gates. Lecture L1.5 explains how to transform circuits using only-NAND or only NOR.

Output V contains only 2-input NAND from the sum of minterms.
Output T using only 2-input NOR from the minimized PoS equation from minilog.

Fig. 1. Symbol and truth table of the circuit to be designed. Be aware that in this symbol, inputs S(1..0) are represented in multi-wire vector form.

Fig. 2. Plan A for inventing and testing circuits from the same initial truth table. (Visio).

Test the circuit using one of these opcions:

- analysis method I on Proteus. The laboratory prototype will contain only 74LS00 and 74LS02 chips.

- analysis method IV on VHDL.

- analysis method II on WolframAlpha.

2. Plan B behavoural approach writting the truth table in VHDL. To verify that your RTL works correctly, use ModelSim functional simulation.

Home Term 22/23-Q1 Contact Electronic devices and companies Software Books Magazines Instruments EED Library EETAC DEEL
Web activa des de 09/2001, @ F. J. Robert, J. Jordana. Web editat amb Microsoft Expression Web 4. El contingut és un complement als materials d'estudi del curs Circuits i Sistemes Digitals disponibles al campus digital Atenea. Llicència:Reconeixement 4.0 Internacional de Creative Commons

Chapter 1 problems

- D1.4 -

Designing circuits using plan A and plan B