UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 1 problems

      - D1.4 -

Designing circuits using plan A and plan B




1. Specifications

Design the combinational Circuit_VT shown in Fig. 1.

1. Plan A structural approach as represented in Fig. 2 based on logic gates. Lecture L1.5 explains how to transform circuits using only-NAND or only NOR.

truth table

Fig. 1. Symbol and truth table of the circuit to be designed. Be aware that in this symbol, inputs S(1..0) are represented in multi-wire vector form.


Fig. 2. Plan A for inventing and testing circuits from the same initial truth table. (Visio).

Test the circuit using one of these opcions:

- analysis method I on Proteus. The laboratory prototype will contain only 74LS00 and 74LS02 chips.

- analysis method IV  on VHDL.

- analysis method II on WolframAlpha.

2. Plan B behavoural approach writting the truth table in VHDL. To verify that your RTL works correctly, use ModelSim functional simulation.