UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

 

1-digit BCD counter with LCD and TMR0 (design phase #3)

P11

FSM + plan X + Interrupts + LCD + TMR0

1. Specifications

Invent the new Counter_BCD_1digit_LCD_TMR0 (design phase #3) with the same Counter_BCD_1digit_LCD (design phase #2) features but connecting the external CLK to the embedded TMR0 peripheral configured as counter. The idea is to free the INT0 (RB0) pin used in the two previous design phases so that it can be used in any other future application while being able to continue counting external events. 

To learn better how o use the TMR0 counter, we can infer two options as two design steps:

(a) The 1-digit BCD counter counts every external CLK pulse.

(b) The 1-digit BCD counter counts every NP = 3 external CLK pulses.  Thus, in general NP is a configurable parameter. 

Counter_BCD_1digit_LCD_TMR0

Fig 1. Symbol of the device to be designed. TMR0 CLK input (T0CKI) is connected to RA4 pin.

 

2. Planning

Most of the planning is inherited from design phase #2 and there is no need to report it again. Let us focus simply on what changes when TMR0 is used as counter attached to CLK pin to replace the external interrupt INT0.

A) Planning hardware

INT0 (RB0) is left unconnected and RA4 (T0CKI) is used as the CLK input for the hardware counter peripheral TMR0. Fig. 3 shows its internal design. The prescaler can also be used to set the number of pulses to count before triggering an overflow interrupt.

TMR0 as a counter

Fig. 2. TMR2 as counter. We can read (poll) the actual TMR0 register value, or we can wait for interrupt on overflow.

The simplified schematic in Fig. 3 shows the block diagram adjusted to this application where the number of pulses counted before TMR0IF are NP = N1·N2.

TMR0 as counter

Fig 3. TMR0 as counter of NP pulses before triggering interrupt.

B) Planning software

The hardware-software diagram has to reflect that the var_CLK_flag variable is obtained using the TMR0 peripheral.

hardware-software diagram

Fig. 4. Hardware-software diagram. 

init_system() includes the TMR0 initialisation as counter. We have to program the configuration bits in T0CON control register accordingly.

Configuring TMR0 as a counter

Fig. 5. TMR0 setup as a counter in init_system().

ISR() is intended to generate var_CLK_flag when TMR0IF is detected (as it was in previous design phases for INT0IF).

ISR

Fig. 6. ISR() flowchart to attend TMR0 interrupts. We have to reload the counter initial value every interrupt event so that only NP pulses are counted before triggering another interrupt. Note how the hardware flag is reset before returning to the main program loop.

 

Organise an MPLABX - XC8 IDE project targeting a PIC18F4520 at location:

C:\CSD\P12\counter_BCD_1digit_LCD_TMR0\(files)

Once it works, plan the design step #2: BCD count will advance every NP = 3 pulses, thus adding var_NP as a parameter. What has to be modified? Discuss the range of NP.

 

3. Development  - 4. Testing  interactively

A) Developing hardware

NOTE: In order to avoid warnings and complications regarding project names and folder path length, we will shorten them.

naming

New project location:

C:\CSD\P12\c_BCD_1d_LCD_TMR0\(files)

Example circuit capture: c_BCD_1d_LCD_TMR0.pdsprj.

hardware connections

Fig. 7. Connect CLK_L terminal to RA4 pin.

B) Developing software

This is the proposed source code c_BCD_1d_LCD_TMR0.c to be compiled along with the LCD library functions in the new project c_BCD_1d_LCD_TMR0_prj. Compile the project to generate executable files.

 

C) Step-by-step testing

Run the Proteus simulator. Do it in step by step mode while watching variables and placing break points, specially for following interrupt flags.

Hardware adapted to PICDEM2+

Fig. 8. The circuit in "run" mode while monitoring the variables in the "watch" window. This top schematic is the same as in design phase #2; users see no differences between design phases #2 and #3.

Pay attention on visualising var_CLK_flag.

Check that the design step #2 works as expected: BCD count will advance every NP = 3 pulses (or any other value).

 

5. Report

This page is an example of report for this design phase #3. Follow this rubric for writing reports.

 

6. Prototyping