UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 2 problems

      - D2.8 -

Electronic keypad lock (version A)

Problems

D2.7

D2.9

1. Specifications

Let us design an electronic keypad lock that requires a numerical code or password in order to unlock the door, thus no need of physical keys. Although they are more expensive than most kinds of locks, your security is well-ensured. It is then important that you keep your numerical code or password safe and difficult for outsiders to guess. In this design we will embed the password "39#" in hardware.

Lock

Fig. 1. The idea of an electronic keypad lock. References about these concepts and commercial products are everywhere, for instance: https://www.nokey.com or https://www.embedded.com/using-finite-state-machines-to-design-software 

Some questions to kick off the project and organise it in four sections. Apply the FSM architecture to this problem.

a) Invent the electronic circuit for conditioning signals and driving the door motor. See Fig. 2.

Electronic circuit

Fig. 2. Schematic for the proposed control system Lock to generate the signal Z for the door motor.

b) As represented in Fig. 3, the latch will open only after having sampled the correct sequence of three numbers.

Sequence

Fig. 3. Sequence for unlocking the latch. 

c) Adapt the FSM architecture to this problem, naming and connecting all signals and inputs and outputs.

d) Infer and draw the circuit's state diagram. Annotate all the state transitions and outputs.

Diagram

Fig. 4. State diagram.

e) Sketch a timing diagram showing the main operations.

f) Draw the state register if coding the machine in one-hot. How many D_FF of memory are used in this problem?

g) Write the CC2 truth table to obtain the outputs of the circuit and its flowchart.

h) Design the CC1 truth table to obtain the next state to go and its flowchart.

i) Write the VHDL file and start an EDA project to synthesise the circuit and obtain results. Inspect the RTL and verify that it looks like your schematic. Check the number of D_FF, print and comment the schematics.

j) Write a VHDL test bench and run the EDA simulation tool to verify your design.

Optional. Other additional features:

k) The system works with a 200 Hz CLK frequency derived from a crystal quartz oscillator of 24 MHz. Add a timer to the keypad lock so that if the right sequence is not entered in 30 s, the system reset automatically.

 

Chapter 2 problems

      - D2.8 -

Electronic keypad lock (version B)

Problems

D2.7

D2.9

1. Specifications

As shown in Fig. 1 let us design another version of electronic keypad lock that requires a 4-digit secret password in order to unlock the door.

- Output lock is driven by a power interface based on 10 s timer, switching transistor and electromechanical relay.

- 7-segment digits show the sequence of input codes while presing keys.

- In this version the secret code is set using 16 switches (for instance "13B7"). This design Keypad_lock.pdsprj solved in Proteus allows playing with the application and studying its internal architecture.

Electronic circuit

Fig. 1. Electronic lock circuit.

- Design this application as a dedicated processorwith FSM and datapath (Fig. 2). CLK_Generator may be required as well to obtain system CLK signals.

Block diagram

Fig. 2. Block diagram as a dedicated processor. 

- Design or find in tutorial examples all the components required for the datapath.

- Design the FSM using for instance the state diagram represented in Fig. 3 deduced from the Proteus circuit. OPEN = '1' only at state S10; other states  OPEN = '0'; CLR_REG = '1' only at S10 and S11; other states '0'. Other signals not indicated are 'x'. 

State diagram

Fig. 3. State diagram.

- Another design option to simplify a bit the datapath from the one studied in the Proteus example, is to input keys as in a calculator, shifting digits from right to left. A single control signal LD from the FSM will load and shift input data. After having captured 4 digits

Another alternative datapath

Fig. 3. An alternative datapath for capturing and left shifting.