UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 2 problems

     - D2.12 -

 Electronic roulette (counters version)




1. Specifications

Let us design a synchronous two digits BCD modulo 37 [00, 01, 02, €, 09, 10, 11, €, 36, 00, 01, €] up and down counter for an electronic roulette as shown in Fig. 1. We will follow structural VHDL plan C2 using EDA tools and counter chaining and truncation techniques. 


Fig. 1. Electronic roulette. The wheel have a zero (house edge), and numbers from 1 to 36. The odds of winning are thus 37 to one (2.7%).

The building block for counting is our Counter_mod16 represented in Fig. 2 and other combinational components and logic. A decoder will be required to translate BCD to one-hot code for driving high the 37 LED.


Fig. 2. Counter_mod16 symbol and function table.

Some questions to kick off the project and organise it in four sections.

a) Draw the symbol and the top schematic of the application Roulette. Fig. 3 may help you. For example, UD_L may be connected to '1' letting the system count only UP, and CE may be the roulette play (P) button generating BCD codes while kept clicked.

Fig. 3. Counter_mod16 symbol and function table.

b) Sketch a timing diagram showing how the circuit operates.

c) Phase #1. Invent the units up counter [0, 1, 2, €, 8, 9, 0, 1, €] using count truncation.

d) Phase #2. Invent the BCD up counter modulo 37.

e) Phase #3. Enhance the previous design so that it can be reversible (up and down).

f) Write the VHDL files and start an EDA project to synthesise the circuit fora FPGA target chip and obtain results. Inspect the RTL and verify that it looks like your schematic. Check the number of D_FF usied in this application, print and comment the schematics.

g) Write a VHDL test bench and run the EDA simulation tool to verify your design.

h) CLK signal. Users have to see how the wheel of LED is spinning while the play button is kept pressed. Thus, let us imagine that turning on and off all the 37 LED takes about 1.5 s. Design a  CLK generator to practically implement a 55.5 Hz squared waveform from a 50 MHz crystal oscillator.


Some diagrams to help approaching solutions.

Decade counter

Fig. 4. Basic up decade counter construction.


Modulo 37

Fig. 5. The idea of a BCD counter modulo 37 tand the logic behind count truncation.