UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 1 problems

      - D1.8 -

16-bit comparator for radix-2 numbers

Problems

D1.7

D1.9

Specifications

Build the 16-bit radix-2 comparator Comp_16bit represented in Fig. 1 using the parallel tree expansion plan C2.

Symbol Comp_16bit

Fig. 1. Comp_16bit symbol.

Specifications include: symbol, truth table, data range, example timing diagram and comparison operations, example commercial chip, etc.

Comp_16bit target chip is one the following:

- MAX II EPM2210F324C3.

- Cyclone IV EP4CE115F29C7

- Calculate the propagation delay in a given signal transition using gate-level simulations.

- Calculate the circuit's longest propagation delay and maximum speed for a given target chip.

 

2. Planning

The proposed architecture for Comp_16bit is represented in Fig.2.

Tree comparator

Fig. 2. 16-bit tree comparator network adapted from this reference book: Ercegovac, M., Lang, T., Moreno, J. H., "Introduction to Digital Systems", John Wiley & Sons, 1999). It includes slides: Chapter 10 is on arithmetic circuits. This is Fig. 10.17 in the referenced book slides.

Comp_4bit component is designed using a chain of expandable Comp_1bit, which can be implemented selecting one the following plans already available in P3:

- Comp_1bit plan A (minimised equations from the truh table in the form of PoS or SoP)

- Comp_1bit plan B (behavioural interpretation of the truth table)

- Comp_1bit plan C2 based on the method of multiplexers (MoM)