UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

P1 design

P2: standard logic circuits: multiplexer, decoder, etc. and VHDL flat single-file design (plan A, plan B)


Resources in lectures and labs:  L2.1 Lab2, L2.2 Project objectives

Highlighted project: MUX_8 plan A: structural single-file VHDL (flat) design

1. Specifications

Design a MUX_8 in a programmable logic device (PLD) target chip with characteritics similar to the classic 74HCT151 chip, following structural plan A using our VHDL design flow and EDA tools for developing and testing.

Chip's logic family (technology), whichever it is TTL, LS, S, CMOS, AS, HC, HCT, F, etc. is not important because the circuit  will be targeted for a PLD from Intel, Xilinx or Lattice Semiconductor. Thus, only chip's functionality is considered.


Fig. 1. Package and pin enumeration of classic 74HCT151 chip.

We have to interpret and rename the pins because every company has its own way to name inputs/outputs and organise their product datasheet (Nexperia, Toshiba/Renesas, ON semiconductor, etc.); thus, in CSD we have decided to use our own naming style and rewrite the truth table accordingly. For instance, the pin 12 will be always our input Ch7, an so the same with all the other pins. 

Examine Texas Instruments 74HCT151 datasheet and represent symbol and truth table, renaming inputs and outputs as shown in Fig. 2.


Fig. 2. Symbol adapted from datasheets. A multiplexer is a data selector. 

In Fig. 3 is represented the circuit's truth table.

truth table

Fig. 3. Truth table. Twelve inputs means 4096 binary combinations.

Finally, in Fig. 4 there is an sketch of a timing diagram.

timing diagram

Fig. 4. Example of a timing diagram sketch  timing diagram to demonstrate how the circuit works for different inputs and so, be able to translate it later to VHDL as a testbench.

Find and study similar products, like MUX_16, MUX_4, MUX_2 and also demultiplexers.

Other single-file flat VHDL projects

Plan A: structure, equations Plan B: behavioural, truth table, algorithm
Dual_MUX_4 Dual_MUX_4
Dec3_8 Dec3_8
Hex_7seg_decoder Hex_7seg_decoder
Enc_10_4 Enc_10_4







- (optional: MUX_8 plan C1, only for demonstration purposes; better solved using plan C2 as explained here:MUX_8.)


2. Planning

Plan A and B covered in L2.1. and Lab2.

In order to implement MUX_8 in a single-file VHDL project using plan A we have to find equations from circuit's truth table.

plan A
Fig. 5. Plan A proposed schematic with equation SoP to be translated into VHDL in the next section.

1.- Use a VHDL description of a minimised SoP or PoS logic equations. (Why the canonical maxterms or minterms are not recommended in this plan?). Find minimised equation PoS or SoP running Minilog.

2.- Project location. For instance, you can seve the project based on SoP here:                                         


and the project based on PoS here:


3.- Find a similar VHDL circuit with an architecture that uses logic equations to copy and adapt.

4.- Write down the VHDL file MUX_8.vhd that contains an architecture of the circuit based on equations.


3. Development

Name the project MUX_8_prj and use one of the EDA tools to implement it selecting a target programmable chip (sPLD, CPLD or FPGA) from our laboratory training boards.

NOTE: Do not write VHDL code without the corresponding schematic / equation / diagram / flow chart / algorithm from the previous planning section. Here in CSD, VHDL source file is always a direct translation of your sketches represented in pen-and-paper. Submitted VHDL files, project developments and testing will not be marked unless they go accompanied by specifications and planning discussion.

1.- Write VHDL files. The entity name is related to the symbol in Fig. 2. Note that in this project channel inputs are not considered a vector but individual wires.

NOTE: Use in CSD the Notepath++ enriched text editor, a very convenient free tool for writing VHDL and C files. Another editor is Scriptum from the company HDL Works.

Fig. 6. Entity descrition of the entity is the same for all design plans. 

Find structural equations and stuff in this similar tutorial on a Dual_MUX_4. You will require the files MUX_8.tbl, MUX_8.equ to find a simplified equation.

 This is a file MUX_8.vhd that correponds exactly to the symbol, including Y_L output as well based on SoP.


2.- Synthesise the circuit's architecture accordingly to the plans A.

Start an EDA tool project for a sPLD/CPLD/FPGA chip MUX_8_prj and obtain the synthesised circuit.

Print, analyse and comment the computer generated RTL and technology views or schematics of the circuits.


Fig. 8. This RTL schematic of a MUX_8 is from ON Semiconductor datasheet. Your project has to generate something similar when following plan A.

What about RTL and technology views when comparing plan A and B?


4. Testing

To test the solution whatever it is from plan A, plan B or plan C1, use the same test bench because even if you have different architectures, we use always the same entity definition under test. The testbench fixture containing the main ideas and concepts involved in this schematic is represented in Fig. 7.

testbench fixture
Fig. 7. Testbench VHDL schematic.

1.- Geenrate the template of the VHDL simulation testbench. The name of the file will be: MUX_8_tb.vhd (if the tool generates a MUX_8.vht, simply rename and copy it at project folder).

2.- Start an EDA VHDL simulator project to verify the Device-Under-Test (DUT) using a VHDL simulator test bench.

This is an example of testbench MUX_8_tb.vhd where inputs have been stimulated with logic values. Copy and paste to your design only constant Min_Pulse and input signals stimulus proces. Testbench VHDL simulation stimulus is the translation to VHDL of the timing diagram in Fig. 4.

3.- Start the simulation process with only a few input vectors (from the timing diagram sketch in the specifications) to see if the whole simulation process works and you are able to watch correctly input and output signals activity. 

4.- Verify applying sufficient test vector that the device works as expected (verify how the information of each channel is selected). Print the timing diagram screen and add comments on the signals to show how the device works.

 In Fig. 8 there is an example of commented  test bench results from the logic analyser (wave) available in the EDA tool simulation tool. Use coloured pens.

test example

Fig. 8. Example of a timing diagram produced by the simulator with some mandatory comments and discussion on the way the circuit works.

5. Report

Special attention has to be paid in annotating all the necessary steps to carry on the design process flow of a circuit using VHDL synthesis and simulation tools. This design flow will be repeated once and again from P2 to P8. 

Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources. 


6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works. More notes in this lesson about target chips sPLD, CPLD and FPGA.