UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

PLA6

Q&A

PLA7: Designing large counters, registers, dedicated processors

PLA9

Lab7
NOTE: This post lab assignment must be solved only after having completed successfully lab session Lab7 because you will copy and adapt materials from it.

Specifications: BCD counter modulo 50k

We aim to design a BCD counter for a commercial digital mini pocket scale (Chip1 in Fig.1). The scale has to range up to 500 g and is equipped with a high accuracy load cell sensor with 0.01 g sensitivity. This PLA is adapted from problem D2.16 where you will find questions and ideas.

The maximum weight before overflow is 499.99 g and thus a Counter_BCD_mod50k is required (decimal point position has no effect on counting).

Scale and datapath

Fig 1. Electronic digital scale and its datapath for measuring mass with 0.01 g resolution.

Find information on how the internal circuit of the scale may be conceived. For instance, it may contain a strain gauge load cell sensor in Wheatstone bridge configuration, signal conditioner (instrumentation amplifier), voltage reference circuit, dual-slope integrating analogue to digital converter (operational amplifiers, comparator, FSM and a datapath like the one represented in Fig.1 which includes Counter_BCD_mod50k, Data_reg20bit and Hex_7seg_decoder) and 7-segment displays.

Organise the design of the Counter_BCD_mod50k using plan C2 and chaining and truncation techniques based on our universal component Counter_mod16.

Project location:

C:\CSD\P7\PLA7\scale\(files)

Specifications: BCD down counter modulo 24

Our goal is to design an hour counter to be used in a real-time clock device. Fig. 1 represents the symbol and function table. This PLA is adapted from problem D2.17 where you will find questions and ideas.

Symbol

Fig 1. Symbol for the proposed entity.

Let us use our plan C2 to build this Counter_BCD_mod24 chaining and truncating Counter_mod16 blocks. 

 CLK signal. Design a CLK_generator to implement a 250 Hz squared waveform from a 50 MHz crystal oscillator.

 Project location:

C:\CSD\P7\PLA7\mod24\(files)

 

Specifications: roulette using shift registers

Let us design an electronic Roulette containing 37 LED as shown in Fig. 1 based on shift registers. We will follow structural VHDL plan C2 using EDA tools and module expandability techniques. This PLA is adapted from problem D2.13 where you will find questions and ideas.

Roulette     Symbl

Fig. 1. Electronic roulette. The wheel have a zero (house edge), and numbers from 1 to 36. The odds of winning are thus 37 to one (2.7%).

Some ideas to start the project:

- Use Shift_reg_4bit as the basic component.

- Implement a FSM to control the Play button and the Shift_reg_37bit. The wheel is spinning while Play button is kept clicked.

- CLK signal. Users have to see how the wheel of LED is spinning while the play button is kept pressed. Thus, let us imagine that turning on and off all the 37 LED takes about 1.5 s. Design a CLK_generator to practically implement a 55.5 Hz squared waveform from a 50 MHz crystal oscillator.

Project location:

C:\CSD\P7\PLA7\roulette\(files)

 

Specifications: BCD up counter modulo 60

Our goal is to design an minute or seconds counter to be used in a real-time clock device. Fig. 1 represents the symbol and function table. It is for counting using BCD code from 00 up to 59. This PLA is adapted from problem D2.18 where you will find questions and ideas.

Symbol

Fig 1. Symbol for the proposed entity.

Let us use our plan C2 to build this Counter_BCD_mod60 chaining and truncating Counter_mod16 blocks. 

CLK signal. Design a CLK_generator to implement a 12.5 kHz squared waveform from a 50 MHz crystal oscillator.

Project location:

C:\CSD\P7\PLA7\mod60\(files)

 

Example of individual assignments
  Circuit   PLD target chip
Group 1 BCD counter modulo 50k   Cyclone IV
Group 2 BCD down counter modulo 24   MAX II
Group 3 Roulette uisng shift registers   MAX II
Group 4 BCD up counter modulo 60 Cyclone IV
Group 5 ··· ···
··· ··· ···

 

P_Ch2 marking grid for pprojects PLA4, PLA5, PLA6 and PLA7

Work assessments to be carried out in laboratory sessions (individual):
  PLA4 PLA5 PLA6  
  1p 2p 2p  

 

PLA7 handwritten report and video presentation (group):
  PLA7    
Video Report  
  2p 3p    

Notes on lab assessment: student grades are not simply reflecting report or video quality, but implicitly, they include laboratory participation, questions and answers, problem solving skills, attendance and punctuality, active attitude and group work.

Follow this rubric for writing reports.

Reflect and give us your group feedback on what you learned in chapter 2 (from P5 to P8). Add a short paragraph in the final section of your PLA7 discussing aspects that you consider positive and negative.