Digital Circuits and Systems - Circuits i Sistemes Digitals (CSD) - EETAC

Laboratory

Laboratory 11: peripherals: [P11] LCD, [P12] TMR0 + dedicated processor

Timer. Phase #1: time-base with external CLK phase #2: LCD phase #3 : internal TMR0

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This is the group post lab assignment PLA10_11 to be submitted at Atenea before the due date. Study and execute in your computer this LAB11 and the previous LAB10 tutorials before attempting to solve this post lab assignment.

3.7.2. Examples: Timer

3.7.2.1. Timer (design phase#1)

This laboratory project is for adapting a basic timer circuit organised as a dedicated processor in P8 (datapath & control unit) to a mC PIC18F46K22. Timer's datapath is conceived as a RAM variable driven by an external CLK (50 Hz) signal connected to an external interrupt (INT1) source. This external CLK is the time-base (TB) of the application defining a time resolution of 20 ms.

1. Specifications

Design phase #1: Design a fixed timing period timer as shown in Fig. 1.

Fig. 1. Timer symbol.

Timing period: TP = 18.5 s, as represented in Fig. 2.
A switch RT to select two modes of operation: re-triggerable and non-retriggerable (consider planning two design steps).
External 50 Hz CLK (INT1) time-base. TB = 20 ms.
Trigger control signal push-button.
LED connected to Timer_out to visualise the timing period duration.
C language, coding in FSM style, dedicated processor approach.
Microcontroller PIC18F46K22.
MPLABX IDE + XC8 compiler + Proteus
CSD_PICstick board for prototyping experimentation.
VB8012 compact instrument for measurement and product characterisation.

We can easily imagine two design steps in this phase:

- Step #1. Basic non-retriggerable timer as for the the classic chip 74LS121. These are other similar classic timer circuits. Thus, we can draw the symbol in Fig. 1 without the RT input signal.

- Step #2. Retriggerable (RT = '1') and non-retriggerable (RT= '0') as for the classic chip 74LS122/123. This control signal RT is a switch to be polled (read or captured) connected to a given port pin, for example RA4.

Fig. 2. a) Waveform in non-retriggerable mode of operation. b) Retriggerable mode of operation where it is possible to keep Timer_out high forever if the user clicks Trigger repeatedly before the timing period ends. This particular circuit application has another widely used name: watchdog timer.

2. Planning

Fig. 3 below shows a dedicated processor design for this timer. The FSM has to be able to attend trigger active edges to start operation and control the datapath, for instance a radix-2 up counter modulo 65536 (16-bit). In this way, for a TPD_CLK = 20 ms used as time base TB, we can generate a Timer_out signal that will last up to 21 min and 50 s.

Fig. 3. Example dedicated processor to perform the timer function as it could have been designed in Chapter 2 (L8.1).

Study other materials, for instance these notes on how a programmable timer can be planned as in Chapter II using VHDL and FPGA/CPLD devices. Review as well the P8 highlighted programmable timer Timer_MMSS that is more complex but with a similar organisation.

Therefore, let us adapt such structures to a microcontroller.

A) Planning hardware

Determine where to connect the crystal oscillator (OSC), the master clear active-low or reset push-button (MCLR_L) control signals, RT, Trigger_L, time base CLK, and the output Timer_out.

Fig. 4. Example of hardware connections.

The interrupt-driven Trigger_L signal is a pushbutton connected at RB0/INT0.

The interrupt-driven CLK external oscillator connected to RB1/INT1 is used to generate a time-base TB = 20 ms from which we will count "real-time".

B) Planning software

Draw the hardware-software diagram imagining which mC resources may be connected to count real time.

Fig. 5. Hardware-software diagram. The interrupt service routine ISR() will generate two flag variables to run the FSM.

List the RAM variables required and their type. Which variables will be flags as we name them attached to interrupts?

Fig. 6. RAM variables.

For instance, a good question to see the adaptability of this architecture: what would be the datapath structure if we like to count for a long timing period of TP = 2.5 h?

Draw the state diagram to run the FSM in control of the application. The external CLK interrupt (var_CLK_flag) will be necessary (enabled) only when timing.

Fig. 7. Proposed state diagram for the FSM. The system is either idle or timing. However, peripherals and operational devices will require set up and stop extra states to prepare them to work properly. Most of the mC peripheral devices may be kept disabled or even switched off when they are not required.

Fig. 8 shows our CSD flowchart to organise the software. The main loop will include the datapath() function running only when timing.

Fig. 8. General software organisation. ISR() will determine which is the interrupt source: trigger button (INT0) or external CLK (INT1). Datapath function for counting CLK periods will not be used when IDLE.

Program init_system() function, configuring ports and interrupts INT0 and INT1.

Fig. 9. These are the data direction registers (TRIS) to configure the ports.

PORTB pin 0 is INT0, the Trigger_L push-button active-low to start timing

PORTB pin 1 is INT1, the external oscillator CLK time-base TB.

PORTA pin 4 is the the switch RT to select between the two modes of operation.

PORTE pin 0 is the the output Timer_out.

Unused port pins are configured by default as outputs.

Program state_logic() so that all state transitions in Fig. 7 are implemented. Draw the truth tables and flowcharts as we usually do applying plan B.

Fig. 10. State logic truth table and its equivalent behavioural flowchart from which C instructions are inferred directly without difficulties.

Program output_logic(). Truth tables and flowcharts. As seen in Fig. 6 hardware-software diagram, output logic has to generate Timer_out circuit's output and control signals for managing the datapath counter.

Fig. 11. Output logic. Truth table and flowchart.

Program datapath() as a P7 counter solved now in software.

Fig. 12. Datapath is a counter described using RAM variables. Be aware that executing assembly instructions requires some μs, consequently introducing some systematic error if what we have in mind is measuring real-time.

Write ISR() flowchart. so that the computer program can be sensitive to events such CLK rising edge and trigger button falling edges.

Fig. 13. ISR() flowchart.

Program read_inputs(), write_outputs(). Truth tables and flowcharts.

Fig. 14. Read_inputs() captures RT value when executed. This value is saved in a convenient RAM variable var_RT.

Fig. 15. Write_outputs() copies var_Timer_out to the RE0 port bit.

Target chip PIC18F46K22. Project location:

C:\CSD\P12\Timer\(files)

3. Dev. & 4. test

A) Developing hardware

The basic timer represented in Fig. 16. "Timer.pdsprj" hardware.


	Fig. 16. Timer circuit captured in Proteus an the microcontroller connections to specific pins.

B) Developing software

Source file example "Timer.c" containing the translation of all planned flowchart. Add the "config.h" header to your project.

Run the microcontroller's IDE to develop and compile the C code to obtain executable files for the target PIC18F46K22.

C) Step-by-step testing

The idea is, as usual, write and run a bit of code with both windows, the hardware Proteus environment and the software IDE running simultaneously for easy debugging. Use watch window and break points to control the program sequence and monitor RAM variables of interest for each function.

Fig. 17. Basic timer running while watching RAM variables.

Questions:

Use breakpoints to measure with precision the timing period TP.
Modify timing period to TP = 3.25 s. In this application the key point is the timing period precision. Is it 3.244 s or 3.246 s?
What can be done to improve the time resolution to 100 ms? Is it even possible to reach such low value?

5. Prototype

Board CSD_PICstick . Target microcontroller: PIC18F46K22. Tools: MPLAB X + XC8 + Proteus + VB8012 compact instrumentation.

Measure the circuit timing period TP using the VB8012 logic analyser?
How to visualise the 8 most significant bits of the internal datapath variable var_Counter_mod65536(9..2) using the VB8012 logic analyser?

6. Report

Follow this rubric for writing reports.

Lab10

Laboratory

Laboratory 11: peripherals: [P11] LCD, [P12] TMR0 + dedicated processor

Timer. Phase #1: time-base with external CLK phase #2: LCD phase #3 : internal TMR0

Lab AR

top

3.7.2.2. Timer_LCD (design phase#2)

Timer enhanced with an LCD peripheral to print ASCII messages (text and numerical data) on the screen.

1. Specifications

Design phase #2: Design a fixed-time timer (for instance 18.5 s) adding an LCD screen for representing information. The symbol is represented in Fig. 1.


Fig. 1. The timer symbol and basic waveform in non-retriggerable mode of operation.

Features:

- Same features as in design phase #1 Timer above.

- In a first step #1 information may be simply ASCII messages, in a second step #2, information may include dynamic data such time in seconds while down counting.

2. Planning