UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Lab 10

Laboratory

Laboratory 11: peripherals: [P11] LCD, [P12] TMR0 + dedicated processor

 Timer. Phase #1: time-base with external CLK        phase #2: LCD        phase #3 : internal TMR0

LAB_AR

[9 Dec]

This is the post lab assignment PLA10_11. 

3.7.2. Examples on how to implement mC applications. Timer.

3.7.2.1. Design phase #1: Timer

This laboratory project is for adapting a basic timer circuit organised as a dedicated processor in P8 (datapath & control unit) to a mC PIC18F46K22. Timer's datapath is conceived as a RAM variable that will count pulses from an external CLK (50 Hz) signal connected to an external interrupt (INT1) source. This external CLK is the time-base (TB) of the application defining a time resolution of 20 ms.

Project tutorial #1: Timer

 

3.7.2.2. Design phase #2: Timer + LCD

Timer enhanced with an LCD peripheral to print ASCII messages (text and numerical data) on the screen.

Project tutorial #2: Timer_LCD

 

3.8.3. Examples: Timer (continuation)

3.8.3.1.  Design phase #3: Timer + LCD + TMR0

Here we will discuss how the functionality assigned to the RAM variable counter and the time base circuits in the datapath can be replaced by the peripheral TMR0 embedded in the microcontroller.

Project tutorial #3: Timer_LCD_TMR0