UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL


P7: standard sequential circuits: counters, data and shift registers


Resources in lectures and labs: L7.1, Lab7, L7.2 Project objectives

Highlighted project: Counter modulo 24 with BCD outputs (Hour_counter)

1. Specifications

Our goal is to design an hour counter to be used in a real-time clock device to count hours in mode AM/PM when M = '1') and mode 00 - 23 when M = ‘0’. Fig. 1 represents the schematic diagram of the application when connected to 7-segment digits.

Let us use our plan C2 to build this counter BCD modulo 24 (hour_counter), chaining Counter_mod16 blocks.


Fig 1. Symbol of the counter BCD modulo 24 (hour_counter). The schematic shows how this block is used when counting hours in a real-time clock project.

Explain the function table of the Hour_counter discussing the different modes of operation.

Draw an example of timing diagram. How many states will the Hour_counter contain?

Timing diagram

Fig. 2. Example of timing diagram when M = '0' (representing hours from 00  to 23 format).


Other similar projects:

As usual, we recommend analysing tutorials to get enough experience to tackle this Hour_counter project: 

- Counter_mod16, 4-bit universal binary counter using plan Y. This is a super powerful component.

- Data_reg_4bit, 4-bit data register using plan Y

- Shift_reg_4bit,  4-bit shift register using plan Y

- Counter_BCD_1digit, 1-digit BCD counter using plan X

- Counter_BCD_1digit, 1-digit BCD counter using plan Y

- Counter_BCD_mod100 in Proteus, plan C2, chaining two 1-digit BCD counters

- Counter_mod12 to explains plan X, plan Y and plan C2.


2. Planning

Organize the internal architecture of the Hour_counter based on the use of universal 4-bit binary counters (Counter_mod16) and combinational circuits and logic gates.

This is the full discussion and the project location:


How many VHDL files will be required to complete the Hour_counter?

How many D_FF this project will contain?


3. Development

Translate the hierarchical top schematic to VHDL. Use the Counter_mod16 as component.

Start an EDA synthesis project for a given target PLD (any CPLD or FPGA available in the laboratory). Inspect the project summary. Inspect the RTL and technology views. Comment them and check the number of DFF used.

This is the complete example in VHDL of the Hour_counter, so you can run and analyse it.  


4. Testing (functional). Does the machine that we have invented work as expected?)

Start the test bench template and add the CLK and inputs activity translating the timing diagram in Fig. 2. Make all time values relative to the CLK_Period constant. 

Run a functional simulation to verify the correctness of the project.

Fig. 3 shows how a functional simulation of the Hour_counter module can be performed. In this case representing the waveforms for M = '1' when the circuit works in AM-PM mode. 

Fig 3. Hour_counter waveforms in funtional simulation for M = '1'.


5. Testing  (gate-level). What is the maximum counting speed?

Run a gate-level timing simulation to measure the maximum speed of the counter deduced from the propagation time from CLK to output (tCO).



6. Report

Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources . 


7. Prototyping

 Choose a laboratory experimentation board like the NEXYS 2 from Digilent. Assign pins and build and check the prototype Hour_counter_top adding the necessary chips and modifications. Pay attention on how the 7-segment digits are wired.