upc eetac_1

Project P7 on standard sequential circuits based on FSM: counters, data and shift registers

Counter modulo 24 with BCD outputs

1. Specifications

Counter modulo 24 (hour_counter) based on chaining Counter_mod16 blocks. Selectable 2 output codes: AM/PM and 00-23.

Icon timing diagram

Fig 1. Symbol of the Hour_Counter and the way it is applied for counting hours in a real-time clock. Example of a timing diagram when M = '0'

System specifications (the Problem 7.8 in the collection).


Learning materials:

- Design of a binary synchronous counter with a small number of states like a FSM in P6 (the Plan A below). Unit 2.3

- Design of a binary synchronous counter of a large number of states like a FSM (arithmetic operations, the Plan B below). [Reorganising the former Unit 2.5, here in this guided problem there is the Counter_mod16 using the same strategy, and here you are its simulation in Proteus].

- Design of a synchronous data register (FSM strategy). [Reorganising the former Unit 2.7, in this guided problem there is a similar device].

- Design of a synchronous  universal shift register (FSM strategy). [Reorganising the former Unit 2.10].


2. Planning

The project's plan is described in the  Problem 7.8. These are some notes and the full discussion.  And this is the project location:

<local drive>/CSD/P7/Hour_counter/files  

However, better if you try to analyse the following examples explained through a sequence of tutorials so that you get enough experience to tackle this Hour_counter project.

1. Solve the Problem 7.7 , a counter modulo 12, using the three following strategies.

- Plan A: FSM strategy as in P6 (naming all the states and State_type signals)

Counter_mod12 architecture

Fig. 2. FSM to implement the Counter_mod12 as a flat design.

As in P6 and in most of the projects when designing a FSM you must follow this sequence: 

- Function table, symbol, timing diagram and other required specifications.

- Draw the state diagram of the Counter_mod12 and infer the number of registers required in this project when encoding in binary sequential, Gray or in one-hot.

- Particularise the general FSM topology to this problem. To which block (CC1, CC2, state register) is connected every input and output? Which is the number of bits  r required for coding the current and next state signals [r = number of states if one-hot; r = (1/log2)·log (number of states) if binary or Gray]?

- Deduce the truth table of the CC1 and CC2 and their corresponding flow charts.

- Write the VHDL code of the finite state machine adapting an example from our web. Project folder location and file names:

<local drive>/CSD/P7/Counter_mod12_A/Counter_mod12.vhd, etc.

- Start an EDA synthesis project and inspect the RTL and technology views. Comment them and check the number of DFF used.

- Run a functional simulation and (optionally) a gate level simulation to measure the maximum speed of the counter deduced from the propagation time from CLK to output (tCO). 


- Plan B: FSM strategy using the VHDL arithmetic library and std_logic_vector signals. A discussion.

<local drive>/CSD/P7/Counter_mod12_B/Counter_mod12.vhd, etc.  


- Plan C: Hierarchical design using multiple VHDL files and components. The idea is truncating a larger counter like the Counter_mod16 explained below in 2

<local drive>/CSD/P7/Counter_mod12_C/Counter_mod12.vhd, Counter_mod16.vhd, etc.


2.- In order to implement the Plan C above, it is necessary to develop the component Counter_mod16 first, which is a synchronous (CLK) reversible (UD_L) expandable (CE and TC16) 4-bit binary counter type 74ALS169 with parallel (LD, Din) inputs. This last feature allows the component to be a 4-bit data register. The complete project is described in the Problem 7.3 of our collection. This is the plan conceived as a single file FSM and using the Plan B methodology depicted above.


Fig. 3. Symbol of the Counter_mod16. And some additional ideas (1), (2), (3).


3. Development

Naturally, each plan above has its own development so that you obtain the corresponding RTL and technology schematics. Examine and annotate them with comments and check whether the number of DFF is correct.

Some example of files for developing the circuits:

- This is the Counter_mod12 VHDL file when using the Plan A.

- This is the Counter_mod12 VHDL file when using the Plan B.

- These are the Counter_mod12 files when using the Plan C including the component Counter_mod16.

- This is the complete Counter_mod16 VHDL description in case you like to run the EDA tools for synthesising and testing. 

- This is the complete example in VHDL of the Hour_Counter, so you can run and analyse it.  

4. Testing  (does the machine that we have invented work as expected?)

Start the test bench template and add the CLK and inputs activity translating the timing diagram. Make all the timing relative to the CLK_Period constant. 

Each project has its own test results. However, when solving the same project, for instance the Counter_mod12 by means of different architectures (Plan A, B, C), you know that you can use the same testbench (Counter_mod12_tb.vhd) all the time.

Functional simulation. Run the EDA VHDL tool and demonstrate how the circuit works adding comments to the printed sheet of paper containing the waveforms. Your system may works like the timing diagram discussed in class.

These below are some example timing diagrams from the  test benches:

Test functional
Fig 4. Example of a functional simulation of the counter module 12.

Run the gate-level simulation of the project and measure the maximum frequency of operation. It is worth to know exactly which is the maxim CLK frequency for a given target CPLD or FPGA chip.

gate level
Fig 5. Example of a gate-level simulation of the counter modulo 12 used to measure the parameter tCO.

This is the example simulation of the Counter_mod16 (the example test bench).

Functional, Counter_mod16
Fig 6. Example of a functional simulation of the universal counter modulo 16. The comments in red ink are very important to check whether the circuit works as expected.  


This picture below shows how a functional simulation of the Hour_counter module can be performed. In this case representing the waveforms for M = '1' when the circuit works in AM-PM mode. 

Hour_counter functional test
Fig 7. Hour_counter waveforms for M = '1'.  



5. Report

Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources . 


6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works.


Other similar projects on sequential circuits

- Read the CSD problems collection and other projects on data registers and shift registers.


Other materials of interest