UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 2 problems

      - D2.5 -

Designing a pattern detector (dedicated processor)




1. Specifications

Our aim is to implement a circuit to detect the binary pattern "0110" received from a radio transmitter bit stream at input T. The symbol of which is represented in Fig. 1.

In order to adjust sampling time in the middle of each transmitted bit, the receiver CLK frequency is four times the transmitter frequency.

When there is no transmission, the receiver is sampling '0' and is kept idle.

When the first '1' is detected, output S goes high for one CLK as a flag to indicate that transmissions are starting. The receiver delays two CLK periods and if the value sampled is yet '1', it starts sampling continuously every four CLK periods. This synchronisation mechanism means that the receiver will sample input T values when signal is stable aproximately at half of the transmission period, far away from T signal transitions.

When the pattern "0110" is detected output Z goes high for one CLK period. Two or more adjacent patterns can also be detected as in this bit stream sequence: "01101101101.."

When four '0' are detected consecutively (pattern "0000"), the transmitter has stopped emitting or something went wrong with the bit stream and thus, the receiver must go back to idle.


Fig. 1. Symbol.

Some questions to kick off the project and organise it in four phases:

a) Infer how many resources the circuit may contain and try to draw a state diagram for the circuit's FSM. Fig. 2 shows preliminary draft ideas and discussion on how the circuit may be organised. Can a FSM block do all the work, or in this application other components such comparators and memory devices (shift registers for instance) are also necessary?

Prelimiary ideas

Fig. 2. Initial discussion on the blocks and states that may be involved in our pattern detector.

b) Apply the FSM architecture to this problem and draw the state register based on D_FF. Deduce how many D_FF are required if coding states in binary sequential (radix-2).

c) Write the truth table of CC1 and CC2 and their equivalent behavioural interpretations using flowcharts.

d) Write the FSM VHDL file and connect all the other components in the top structure. Develop the circuit for a MAX II target chip using EDA tools. Inspect the RTL and technology views. How many D_FF registers are used in this application?

e) What is the maximum transmitter CLK if an Intel MAX II CPLD is used as the target chip to implement the prototype?