UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 1 problems

      - A1.6 -

Analysing Circuit_G and designing equivalent circuits

Problems

A1.5

A1.7

Analysis. Obtain the truth table of Circuit_G shown in Fig. 1. Apply analysis method III.

Circuit_G

Fig. 1. Combinational circuit. g = f(a, b, c)

- Deduce the circuit algebraic equation.

- Transform the algebraic expression to SoP (or PoS) using Boole algebra.

- Transform SoP (or PoS) to a sum of minterms (or a product of maxterms). Draw the truth table.

- Draw a timing diagram considering all binary combinations and constant Min_Pulse = 2.3 μs.

- Verify your result using a Proteus circuit simulation (method I) or WolframAlpha (method II).

Design plan A. Design an equivalent circuit for Circuit_G from its truth table deduced above, for example naming it Circuit_G1, minimising using minilog and using only NOR.

sYMBOL

Fig. 2. Combinational circuit. g = f(a, b, c)

Capture your schematic in Proteus using CMOS technology and verify your implementation using WolframAlpha.

Design plan B. Design an equivalent circuit for Circuit_G from its truth table deduced above, for example naming it Circuit_G2, capturing the truth table behaviour as an schematic or as a flowchart.

Circuit_G2

Fig. 3. Combinational circuit. g = f(a, b, c)

Synthesise the circuit in VHDL by means of a Quartus Prime project for a FPGA target chip and verify it simulating a ModelSim testbench.