UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

 

Circuits based on logic gates

P1

Circuit_K analysis


1. Design specifications

 Using Circuit_K truth table written in Fig. 1 invent the following equivalent circuits using gates (plan A):

Symbol
sum of minterms

Fig. 1. Circuit_K to desing. K = f(D1, D0, A, B)

Circuit_K1 - Using the minimised equation product of sums (PoS) from minilog.exe. Check the solution using VHDL.

Circuit_K3- Transform Circuit_K1 and build another version using  only 2-input NAND gates. Check the solution using Proteus.

 

2. Planning the design of equivalent circuits using gates

From the initial specifications in Fig. 1 you can invent/create/infer and test/check/verify several circuits as shown in L1.4

Designing circuits

Fig. 2. Designing two circuits from the same initial truth table.

Concepts about transforming circuits to contain only NAND are explained in lecture L1.5.

 

3. Design development

Using minilog with Circuit_K.tbl the Circuit_K1 based on PoS can be obtained:

C:\CSD\P1\Circuit_K\Circuit_K1\Circuit_K.tbl, etc.

PoS equation
Circuit_K1

Fig. 3. Circuit_K1 PoS equation from minilog.


And modifying Circuit_K1 we can deduce Circuit_K3 in two steps: 1) circuit based on only-NAND; 2) transform all  NAND gates to NAND2.

Circuit ONLY NAND
equations only NAND

Fig. 4. Circuit_K2 schematic consisting of only NAND. And the required transformation of each NAND so it can be implemented using only NAND2 chips.

 

4. Design testing

Testing means to check or verify that the solution is correct and agrees with the initial specifications.

Circuit_K1 based on PoS can be checked using a VHDL project from this translated Circuit_K1.vhd.

C:\CSD\P1\Circuit_K\Circuit_K1\ (files Circuit_K1.vhd, etc.)

PoS
logic diagram

Fig. 5. Circuit_K1 RTL schematic showing the PoS circuit and the truth table verification. 


Circuit_K2 using only NAND (Circuit_K2_equ.txt) checked using WolframAlpha do not work because the equation is too long. Thus the alternative is to use Proteus: Circuit_K3.pdsprj or VHDL.

C:\CSD\P1\Circuit_K\Circuit_K3\(files)

Circuit_K3
simulation

Fig. 6. Circuit_K3 captured in Proteus for truth table verification.

 

5. Design reports

Using pictures, diagrames, sketches, handwritting discussions, etc.