UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

PLA2

Q&A

PLA3: Designing arithmetic and logic circuits using hierarchical multiple-file plan C2

PLA4

Lab3
NOTE: This post-lab assignment must be solved only after having completed successfully lab session Lab3 because you will copy and adapt materials from it.

Specifications

Example of group assignments
  Number, entity to design Plan C2 options Target chip options Test vectors options
Group 1 D1.10 Parking_occupancy #1 RC Adder_4bit #1 #1
Group 2 D1.18 ALU_12bit #2 CLA Adder_12bit #1 #1
Group 3 D1.10 Parking_occupancy #2 CLA Adder_4bit #2 #2
Group 4 D1.18 ALU_12bit #2 RC Adder_12bit #2 #2
         

 

This group submission at Atenea includes the report in a PDF file, the zipped project and also a self-assessment.

Notes on how to write and organise your report:

PLA3 written report sections:  

1. Specifications and theory

Original handwritten materials on symbol, truth table, timing diagram and other explanations on data types and operations to be performed. Include example on how the circuit operate, use the corresponding radix to make for easy interpretation of the operands and results. Explain the meaning and the function of each input and output and the data range.  

2. Planning

Original handwritten explanations and VHDL-ready schematics on how this plan C2 circuit is conceived, the proposed hierarchy of components, signals, number of VHDL files, project folders and names, etc. Explain what is the task assigned to each group member so that everyone is learning everything at the same time you are stydying for exams. Explain how you large project is divided in (1) top entity and (2) components (to be designed separatelly in annexes). Explain which component you will solve (1-2-3-4) firstly to get some practice with the tools and the plan C2 before designing other components or the top entity.

3. Development

Top project development in Quartus Prime for a target FPGA chip. Printings and handwritten discussions of RTL and technology schematics. How many FPGA resources (logic cells, logic elements, etc.) are used?

4.Test and verification

Testbench fixture schematic, proposed stimulus testbench process. Printings and handwritten discussions on results. Add your conclusions on the project and on what has been learned. Remember that your self-assessment is expected to be submitted as well at the Atenea platform. 

5. Annexes

Design and test a given component to learn about the tools and plan C2 before developing the top project. If you invent a new component that is not available in digsys, the best way to report it is as an annex organised as a complete project. If you use the VHDL files from a component already available in digsys, you simply need to describe it in a single sheet as symbol and truth table (specifications).

Notes on video presentations: 10 min. max., 3 - 4 min. each participant.

The idea of the video presentation is different from the written report and has its own particular objective: develop your oral communications skills in our engineering context. Put in motion your communication skills that you will continue to practise and improve through PLA7 and PLA11. We will focus assessment in how you are organising the presentation, how confident you are in front of the camera, time sharing among students, support materials, time distribution and audio and video quality. This is an example of final PLA11 presentation. 

 

Reflect and give us your group feedback on what you learned in chapter 1 (from P1 to P3). Add a short paragraph in the final section of your PLA3 discussing aspects that you consider positive and negative.