UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

PLA2

Q&A

PLA3: Designing arithmetic and logic circuits using hierarchical multiple-file plan C2

PLA4

Lab3
NOTE: This post-lab assignment must be solved only after having completed successfully lab session Lab3 because you will copy and adapt materials from it.

Specifications (radix-2 Comp_16bit)

Build the 16-bit radix-2 comparator Comp_16bit represented in Fig. 1 using the parallel tree expansion plan shown in Fig. 2. Thus, applying plan C2. This PLA is adapted from problem D1.8.

Symbol Comp_16bit
Fig. 1. Comp_16bit symbol.

Specifications include: symbol, truth table, data range, example timing diagram and comparison operations, example commercial chip, etc.

Tree comparator

Fig. 2. 16-bit tree comparator network adapted from this reference book: Ercegovac, M., Lang, T., Moreno, J. H., "Introduction to Digital Systems", John Wiley & Sons, 1999). It includes slides: Chapter 10 is on arithmetic circuits. This is Fig. 10.17 in the given slides reference.

Comp_4bit component is designed using a chain of expandable Comp_1bit as shown in P3 schematics.

Comp_1bit can be implemented choosing between plans already available in P3: Comp_1bit using plan A, Comp_1bit using plan B or Comp_1bit using plan C2 - MoM; your instructor will tell you which.

Comp_16bit target chip is one the following, your instructor will tell you which:

- MAX II EPM2210F324C3.

- Cyclone IV EP4CE115F29C7

Project location:

 C:\CSD\P3\PLA3\Comp_16bit\(files)

 

Specifications (signed integer Int_Comp_16bit)

Build the comparator Int_Comp_16bit represented in Fig. 1 for 16-bit two's complemented (2C) integers.

 Invent the plan after having studied the example Int_Comp_8bit. This PLA is adapted from problem D1.9.

Symbol Int_Comp_16bit
Fig. 1. Symbol.

Specifications include: symbol, truth table, data range, example timing diagram and comparison operations, example commercial chip, etc.

Comp_4bit component is designed using a chain of expandable Comp_1bit (as shown in P3 schematic).

Invent the Comp_1bit using plan C2 based on the method of decoders (MoD). In P3 tutorials we find the Comp_1bit truth table, and in P2 we find the Dec_4_16.vhd component can be used to implement the Dec_5_32 represented in Fig. 2 required in this application.

Dec_5_32
Fig. 2. Designing Dec_5_32 expanding Dec_4_16.

Int_Comp_16bit target chip is one of the following, your instructor will tell you which:

- MAX II EPM2210F324C3.

- Cyclone IV EP4CE115F29C7

Project location:

 C:\CSD\P4\PLA3\Int_Comp_16bit\(files)

 

 
Example of individual assignments (your instructor will indicate you which during lab session)
Top circuit  Plan for component Comp_1bit Target chip Example test vectors
Group 1 Comp_16bit A Cyclone IV 3541, 40387, 202, 33914, 65534, 18
Group 2 Int_Comp_16bit C2 MoD MAX II -32766, -14600,
-12, +18, +27433, +12368
Group 3 Comp_16bit B Cyclone IV ···
Group 4 Int_Comp_16bit C2 MoD Cyclone IV ···
Group 5 Comp_16bit C2 MoM MAX II ···
··· ··· ··· ··· ···

 

 

P_Ch1 marking grid for projects PLA1_1, PLA1_2, PLA2 and PLA3

Work in progress assessments to be carried out in laboratory sessions (individual)
  PLA1_1 PLA1_2 PLA2  
1p 2p 2p

Note Work in progress includes completing tutorials, sample reports, sketches, diagrams, discussions, Q & A, presentations, live demonstrations, results, measurements, etc.

 

PLA3 handwritten report and video presentation (group):
  PLA3    
Video Report  
  2p 3p    

Notes on lab assessment: student grades are not simply reflecting report or video quality, but implicitly, they include laboratory attendance and punctuality, participation, Q & A, problem solving skills, active attitude and group work.

Notes on how to write and organise your report.

Report layout. Example of PLA3 written report layout (one submission per cooperative lab group), a single PDF file:  

1. Specifications and theory

Original handwritten materials on symbol, truth table, timing diagram and other explanations on data types and operations to be performed.  

2. Planning

Original handwritten explanations and VHDL-ready schematics on how this plan C2 circuit is conceived, the proposed hierarchy of components, signals, number of VHDL files, project folders and names, etc.

3. Development

Project in Quartus Prime for a target FPGA chip: Intel Cyclone IV EP4CE115F29C7. Printings and handwritten discussions of RTL and technology schematics. How many FPGA resources (logic cells, logic elements, etc.) are used?

4.Test and verification

Testbench schematic, proposed stimulus testbench process. Printings and handwritten discussions on results.

Add your conclusions on the project done and on what has been learned. Remember that your self-assessment is expected to be submitted as well at the Atenea platform. 

5. Annexes

Design or explanations on components. If you invent a new component, the best way to report it is as an annex organised as a complete project. If you use the VHDL files from a component already available in digsys, you simply need to describe it in a single sheet as symbol and truth table (specifications).

Notes on video presentations: 10 min. max., 3 - 4 min. each participant.

The idea of the video presentation is different from the report and has its own particular objective: develop your oral communications skills in this engineering context. Put in motion your communication skills that you will continue to practise and improve through P_Ch2 and P_Ch3. We will focus assessment in how you are organising the presentation, how confident you are in front of the camera, time sharing among students, support materials, time distribution and audio and video quality.