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Bachelor's Degree in Telecommunications Systems and in Network Engineering |
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Laboratory 2: designing an standard MUX_8. Single-file VHDL (flat) design [P2] Circuit MUX_8 - plan A: structural |
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Individual post lab assignment PLA2 to be discussed next Lab3. Study and execute this lab tutorial before attempting to solve the post lab assignment. |
1.7.2. Multiplexer or data selector
1. Specifications
Design a MUX_8 with characteristics similar to the classic 74HCT151 chip in a programmable logic device (PLD) target chip following structural plan A using our VHDL design flow and EDA tools for developing and testing.
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Fig. 1. Package and pin enumeration of classic 74HCT151 chip. We have to interpret and rename the pins because each company has its own way to name inputs/outputs and organise product datasheets (Nexperia, Toshiba/Renesas, ON semiconductor, Texas Instruments 74HCT151, etc.); thus, in CSD we have decided to use our own naming style and rewrite the truth table accordingly. For instance, the pin 12 will be always our input Ch7, an so the same with all the other pins. The technology of the logic family (TTL, LS, S, CMOS, AS, HC, HCT, F, etc.) is not important because the circuit will be targeted for a PLD from Intel, Xilinx or Lattice Semiconductor. Thus, only the chip functionality is considered. |
Fig. 2 shows our MUX_8 symbol.
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| Fig. 2. Symbol adapted from datasheets. A multiplexer is a data selector. |
In Fig. 3 is represented the circuit's truth table using don't care terms.
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Fig. 3. Truth table. The circuit has twelve inputs, it means 4096 binary combinations. |
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| Fig. 4. Example of a timing diagram sketch to demonstrate how the circuit works for different inputs. This input activity will be translated to VHDL as a stimulus process in the simulation testbench (Fig. 10). |
Find and study similar products, like MUX_16, MUX_4, MUX_2 and also demultiplexers.
In this project we will apply our VHDL design flow using plan A: flat (single-file) structural VHDL project. Take some time studying this specifications and how a structural plan will look like (rec.). Is it possible or easy) to write canonical equations based on minterms or maxterms?
This is the general concept map rec. to design most of CSD circuits.
2. Planning
Fig. 5. may be a sequence of operations for inventing MUX_8 in a single-file VHDL project using plan A.
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| Fig. 5. Planning the development (synthesis) of the circuit. |
The verification of the circuit under test may be carried out following Fig. 6 sequence.
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| Fig. 6. Testing procedure. |
- We have to find equations from circuit's truth table.
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| Fig. 7. Schematic with equation SoP. Output Y_L is implemented using an inverter. Explain what is a port and what is a signal. |
Project location. For instance, you can save the project based on SoP here:
C:\CSD\P2\MUX_8A_SoP\(files)
Alternatively, other students may solve the project using PoS at the location:
C:\CSD\P2\MUX_8A_PoS\(files)
Find a similar VHDL circuit in P2 with an architecture that uses logic equations to copy and adapt.
3. Development
Find minimised equations PoS or SoP running Minilog. This is an example Minilog file MUX_8.tbl capturing the truth table to obtain a simplified equation.
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| Fig. 8. Minilog results in SoP format. |
Find a similar VHDL circuit file in P2 with an architecture that uses logic equations to copy and adapt. This is a VHDL translation source file MUX_8.vhd that corresponds exactly to our plan in Fig. 7 using SoP. The entity name is related to the symbol in Fig. 2. Note that in this symbol channel inputs are not considered as a vector but as individual wires.
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| Fig. 9. Description of the entity is the same for all design plans. |
KEY NOTE in CSD: Do not write VHDL code without the corresponding printed schematic / e equation / diagram / flowchart / algorithm from the previous planning section. Here in CSD, VHDL source file is always a direct translation of your handwritten sketches. Submitted VHDL files, project developments and testing will not be marked unless they go accompanied by specifications and planning discussion. Be aware also about your commitment to academic integrity at the UPC.
Name the project MUX_8_prj and use one of the EDA tools to implement it selecting a target programmable chip (sPLD, CPLD or FPGA) from our laboratory training boards. For instance, use Intel MAX II CPLD EPM2210F324C3.
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| Fig. 10. Project name, location and top entity. Synthesis summary. |
Synthesise your circuit and examine results. Print, analyse and comment the computer generated RTL and technology views or schematics of the circuits.
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| Fig. 11. RTL schematic of a MUX_8 generated by Quartus Prime when using SoP equation. |
Our RTL circuit is not that different from the schematic proposed by vendors like ON Semiconductor. Chip 74HCT151 implements product terms using NAND.
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Fig. 12. For discussion and comparison purposes, this is the schematic of a 74HCT151 MUX_8 from ON Semiconductor datasheet. |
In Quartus Prime we can inspect how the real circuit is implemented attending the chip resources and internal architecture using technology schematic viewer and chip planner tools.
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Fig. 13. Technology view for target chip Intel MAXII EPM2210F324C3. How many resources (logic cells) are used? |
What kind of technology contain this MAXII CPLD? For example, from MAX II 300 pages handbook (page 77) we can calculate noise margins of its input/output buffer elements (IOE). Fig. 14 shows DC characteristics of the LVTTL and LVCMOS I/O standards powered at 3.3 V.
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Fig. 14. Calculate the NMH and NML from these tables. |
4. Testing
To test the synthesised design, whatever it is from plan A, B or C2, we use the same testbench fixture. Even if you have different internal architectures for the UUT (unit under test), the entity definition is always the same, as shown in Fig. 15.
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| Fig. 15. Testbench VHDL schematic fixture. |
Generate the template of the VHDL simulation testbench from Quartus Prime. The name of the file will be: MUX_8_tb.vhd (if the tool generates the file MUX_8.vht rename and move it into the project folder).
This is an example of testbench MUX_8_tb.vhd file representing the translation into VHDL of the schematic in Fig. 15. Waveforms in Fig. 4 are placed in "tb : PROCESS " as example stimulus.
Start an EDA VHDL functional simulation project (ModelSim) to verify the device-under-test (DUT).
Run the simulation process with only a few input vectors to see if the whole simulation process works and you are able to watch correctly input and output signals activity. Add more test vectors to verify how the information of each channel is selected.
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What value are you choosing for Min_Pulse? How long will be necessary to run the simulation for the stimulus represented in Fig. 4?
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How long does it take to simulate the complete truth table imagining that all stimulus vectors have the same duration 2.3*Min_Pulse?
Print the timing diagram screen and add comments on the signals to show how the device works. Fig. 16 shows an example of commented test bench results from the logic analyser (wave) available in the EDA simulation tool. Use coloured pens.
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Fig. 16. Example of a timing diagram produced by the simulator with some mandatory comments and discussion on the way the circuit works. |
5. Report
Follow this rubric for writing reports.
6. Prototyping
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Laboratory 2: Designing an standard MUX_8. Single-file VHDL (flat) design [P2] Circuit MUX_8 - plan B: behavioural |
[16/3] |
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Individual post lab assignment PLA2 to be discussed next Lab3. Solve and study all the details in this lab class before attempting to apply it to solve the post lab assignment. |
1. Specifications
Design a MUX_8 with characteristics similar to the classic 74HCT151 chip in a programmable logic device (PLD) target chip following structural plan B using our VHDL design flow and EDA tools for developing and testing.
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| Fig. 1. Symbol and truth table. | |
In Fig. 2 there is an sketch of timing diagram.
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Fig. 2. Example of a timing diagram sketch to demonstrate how the circuit works for different inputs. Inputs will be translated to VHDL as stimulus signals in the simulation testbench. |
2. Planning
This flowchart explains the main concepts involved in VHDL design flow process.
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| Fig. 3. Plan B sequence of operations. |
Translate the truth table into an algorithm or flowchart (rec.) or schematic for capturing the complete truth table. As shown in Fig. 4 there are always several options to obtain a flowchart.
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| Fig. 4. Plan B flowchart interpretations of the truth table, versions (1) and (3) |
And several options as well to capture the complete truth table in a single statement.
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| Fig. 5. Plan B truth table capture, versions (2_1) and (2_2) |
Each behavioural version will generate a different VHDL file, thus, adapt folder names for saving them:
C:\CSD\P2\MUX_8B1\(files)
C:\CSD\P2\MUX_8B2_1\(files)
C:\CSD\P2\MUX_8B2_2\(files)
C:\CSD\P2\MUX_8B3\(files)
3. Development
Find in P2 a similar circuit designed using plan B with an architecture that corresponds to a truth table or algorithm to copy and adapt.
Translate your algorithm, flow chart or schematic into VHDL in a single file. These are up to four versions: (1) MUX_8.vhd; (2_1) MUX_8.vhd; (2_2) MUX_8.vhd; (3) MUX_8.vhd, accordingly to the plans inferred above.
The entity name and VHDL description is related to the symbol in Fig. 1 and it does not depend on the plan.
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| Fig. 6. The entity description in VHDL is the same for all design plans. |
Start a new project in Quartus Prime, name it MUX_8_prj and select a target programmable chip (CPLD or FPGA) from our laboratory training boards. For instance, use Intel MAX II CPLD EPM2210F324C3, the same used above in plan A for better comparing circuit realisations.
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| Fig. 7. New project in Quartus Prime. |
Synthesise your circuit and examine results. Print, analyse and comment the computer generated RTL and technology views or schematics of the circuits.
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| Fig. 8. Example of RTL (click to expand). Why is this circuit such different from the one in plan A Fig. 11 above? |
As shown in Fig. 9, even for initial source VHDL files based on totally different plans, the same technology circuit is implemented for real in the target chip.
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Fig. 9. Example of technology view. How many resources (logic cells) are used? How different is this circuit from the one represented in plan A Fig. 13 above? |
Discuss advantages and drawbacks of plans A and B.
4. Testing
To test the solution whatever it is from plan A, plan B, plan C1 or plan C2, use the same test bench because even if you have invented different architectures, we use always the same entity under test. The testbench fixture containing the main ideas and concepts involved in this schematic is represented in Fig. 10.
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| Fig. 10. Testbench VHDL schematic. |
Generate from Quartus Prime the testbench template in Fig. 10. Rename it and move it to the project folder. Delete the empty process.
Translate the stimulus signals into a process and set the constant Min_Pulse in Fig. 4. This is a VHDL testbench example MUX_8_tb.vhd from which you can copy only the stimulus process and Min_Pulse constant.
Start an EDA VHDL simulator project to verify the device-under-test (DUT) using the VHDL simulator test bench.
In Fig. 11 there is an example of commented test bench results from the logic analyser (wave) available in the EDA tool simulation tool. Use coloured pens.
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Fig. 13. Example of a timing diagram produced by the simulator with some mandatory comments and discussion on the way the circuit works. |
5. Report
Follow this rubric for writing reports.
6. Prototyping
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