| Laboratory | Laboratory 2: designing a standard MUX_8. Flat single-file VHDL. Plan A - Plan B [P2] Demonstration prototype on standard logic circuits: MUX-DeMUX circuit | [30 Sept] | 
| This is the post lab assignment PLA2_3. | 
1.7.2. 2. Multiplexer or data selector design examples
| Project tutorial #1: Design a MUX_8 using plan A. | 
This is another similar circuit to study and practise: Hex_7seg_decoder.
| Project tutorial #2: Design a MUX_8 using plan B. | 
This is another similar circuit Hex_7seg_decoder.
1.7.3.5. Demonstration prototype MUX-DeMUX
| Project tutorial #3: Prototyping a MUX_DeMUX for laboratory experimentation |