Digital Circuits and Systems - Circuits i Sistemes Digitals (CSD) - EETAC

Laboratory

Laboratory 2: designing a standard MUX_8. Flat single-file VHDL Plan A - Plan B - Prototype

[P2] Circuit MUX_8 - plan A: structural

[6/3]

Individual post lab assignment PLA2 to be discussed next Lab3. Study and execute this lab tutorial before attempting to solve the post lab assignment.

1.7.2. Multiplexer or data selector

1. Specifications

Design a MUX_8 with characteristics similar to the classic 74HCT151 chip in a programmable logic device (PLD) target chip following structural plan A using our VHDL design flow and EDA tools for developing and testing.

Fig. 1. Package and pin enumeration of classic 74HCT151 chip.

We have to interpret and rename the pins because each company has its own way to name inputs/outputs and organise product datasheets (Nexperia, Toshiba/Renesas, ON semiconductor, Texas Instruments 74HCT151, etc.); thus, in CSD we have decided to use our own naming style and rewrite the truth table accordingly. For instance, the pin 12 will be always our input Ch7, an so the same with all the other pins.

The technology of the logic family (TTL, LS, S, CMOS, AS, HC, HCT, F, etc.) is not important because the circuit will be targeted for a PLD from Intel, Xilinx or Lattice Semiconductor. Thus, only the chip functionality is considered.

Fig. 2 shows our MUX_8 symbol.

MUX_8 symbol

Fig. 2. Symbol adapted from datasheets. A multiplexer is a data selector.

In Fig. 3 is represented the circuit's truth table using don't care terms.

Truth table

Fig. 3. Truth table. The circuit has twelve inputs, it means 4096 binary combinations.

Fig. 4. Example of a timing diagram sketch to demonstrate how the circuit works for different inputs. This input activity will be translated to VHDL as a stimulus process in the simulation testbench (Fig. 10).

Find and study similar products, like MUX_16, MUX_4, MUX_2 and also demultiplexers.

In this project we will apply our VHDL design flow using plan A: flat (single-file) structural VHDL project. Take some time studying this specifications and how a structural plan will look like (rec.). Is it possible or easy) to write canonical equations based on minterms or maxterms?

This is the general concept map rec. to design most of CSD circuits.

2. Planning

Fig. 5. may be a sequence of operations for inventing MUX_8 in a single-file VHDL project using plan A.

Fig. 5. Planning the development (synthesis) of the circuit.

The verification of the circuit under test may be carried out following Fig. 6 sequence.

Fig. 6. Testing procedure.

- We have to find equations from circuit's truth table.

Fig. 7. Schematic with equation SoP. Output Y_L is implemented using an inverter. Explain what is a port and what is a signal.

Project location. For instance, you can save the project based on SoP here:

C:\CSD\P2\MUX_8A_SoP\(files)

Alternatively, other students may solve the project using PoS at the location:

C:\CSD\P2\MUX_8A_PoS\(files)

Find a similar VHDL circuit in P2 with an architecture that uses logic equations to copy and adapt.

3. Development

Find minimised equations PoS or SoP running Minilog. This is an example Minilog file MUX_8.tbl capturing the truth table to obtain a simplified equation.

Fig. 8. Minilog results in SoP format.

Find a similar VHDL circuit file in P2 with an architecture that uses logic equations to copy and adapt. This is a VHDL translation source file MUX_8.vhd that corresponds exactly to our plan in Fig. 7 using SoP. The entity name is related to the symbol in Fig. 2. Note that in this symbol channel inputs are not considered as a vector but as individual wires.

Fig. 9. Description of the entity is the same for all design plans.

KEY NOTE in CSD: Do not write VHDL code without the corresponding printed schematic / e equation / diagram / flowchart / algorithm from the previous planning section. Here in CSD, VHDL source file is always a direct translation of your handwritten sketches. Submitted VHDL files, project developments and testing will not be marked unless they go accompanied by specifications and planning discussion. Be aware also about your commitment to academic integrity at the UPC.

Name the project MUX_8_prj and use one of the EDA tools to implement it selecting a target programmable chip (sPLD, CPLD or FPGA) from our laboratory training boards. For instance, use Intel MAX II CPLD EPM2210F324C3.

Fig. 10. Project name, location and top entity. Synthesis summary.

Synthesise your circuit and examine results. Print, analyse and comment the computer generated RTL and technology views or schematics of the circuits.

Fig. 11. RTL schematic of a MUX_8 generated by Quartus Prime when using SoP equation.

Our RTL circuit is not that different from the schematic proposed by vendors like ON Semiconductor. Chip 74HCT151 implements product terms using NAND.

Fig. 12. For discussion and comparison purposes, this is the schematic of a 74HCT151 MUX_8 from ON Semiconductor datasheet.

In Quartus Prime we can inspect how the real circuit is implemented attending the chip resources and internal architecture using technology schematic viewer and chip planner tools.

Fig. 13. Technology view for target chip Intel MAXII EPM2210F324C3. How many resources (logic cells) are used?

What kind of technology contain this MAXII CPLD? For example, from MAX II 300 pages handbook (page 77) we can calculate noise margins of its input/output buffer elements (IOE). Fig. 14 shows DC characteristics of the LVTTL and LVCMOS I/O standards powered at 3.3 V.

Fig. 14. Calculate the NMH and NML from these tables.

4. Testing

To test the synthesised design, whatever it is from plan A, B or C2, we use the same testbench fixture. Even if you have different internal architectures for the UUT (unit under test), the entity definition is always the same, as shown in Fig. 15, and thus the same testbench to apply stumulus can be used again.

Fig. 15. Testbench VHDL schematic fixture.

Generate the template of the VHDL simulation testbench from Quartus Prime. The name of the file will be: MUX_8_tb.vhd (if the tool generates the file MUX_8.vht rename and move it into the project folder).

This is an example of testbench MUX_8_tb.vhd file representing the translation into VHDL of the schematic in Fig. 15. Waveforms in Fig. 4 are placed in "tb : PROCESS " as example stimulus.

Start an EDA VHDL functional simulation project (ModelSim) to verify the device-under-test (DUT).

Run the simulation process with only a few input vectors to see if the whole simulation process works and you are able to watch correctly input and output signals activity. Add more test vectors to verify how the information of each channel is selected.

What value are you choosing for Min_Pulse? How long will be necessary to run the simulation for the stimulus represented in Fig. 4?
How long does it take to simulate the complete truth table imagining that all stimulus vectors have the same duration 2.3*Min_Pulse?

Useful hints in ModelSim. You can order the signals as in the initial sketch in Fig. 4 for a better interpretation of the truth table and simulation result.

Fig. 16. Order the entity input and output ports as in the initial sketch.

You can save and restore this signal setup in a convenient wave.do file, as shown in Fig. 17, so that it can be reused in other simulations of the same entity.

The instrument setup can be saved as a convenient wave.do file in your project folder as shown in Fig. 17 and reused again for other simulations of the same entity.

Fig. 17. Save and restore the instrument setup in a txt file wave.do (its format type is TCL language).

Print the timing diagram screen and add comments on the signals to show how the device works. Fig. 18 shows an example of commented test bench results from the logic analyser (wave) available in the EDA simulation tool. Use coloured pens.

Fig. 18. Example of a timing diagram produced by the simulator with some mandatory comments and discussion on the way the circuit works.

You can change the radix in which signals are represented. For instance, in this MUX_8 circuit, the vector S(2..0) can be displayed in radix-2 or in radix-10, as shwon in Fig. 19 and Fig. 20 below.

Fig. 19. Select the signal of interest S(2..0) to change to binary radix-2 representation.

Fig. 20. Select the signal of interest S(2..0) to change to radix-10 (unsigned decimal).

5. Report

Follow this rubric for writing reports.

6. Prototyping

See at the lab end section 6.

Lab1_2

Laboratory

Laboratory 2: designing a standard MUX_8. Flat single-file VHDL Plan A - Plan B - Prototype

[P2] Circuit MUX_8 - plan B: behavioural

Lab3

[6/3]

Individual post lab assignment PLA2 to be discussed next Lab3. Solve and study all the details in this lab class before attempting to apply it to solve the post lab assignment.

1. Specifications

Design a MUX_8 with characteristics similar to the classic 74HCT151 chip in a programmable logic device (PLD) target chip following structural plan B using our VHDL design flow and EDA tools for developing and testing.



Fig. 1. Symbol and truth table.

In Fig. 2 there is an sketch of timing diagram.

timing diagram

Fig. 2. Example of a timing diagram sketch to demonstrate how the circuit works for different inputs. Inputs will be translated to VHDL as stimulus signals in the simulation testbench.

2. Planning

This flowchart explains the main concepts involved in VHDL design flow process.

Fig. 3. Plan B sequence of operations.

Translate the truth table into an algorithm or flowchart (rec.) or schematic for capturing the complete truth table. As shown in Fig. 4 there are always several options to obtain a flowchart.

Fig. 4. Plan B flowchart interpretations of the truth table, versions (1) and (3)

And several options as well to capture the complete truth table in a single statement.

Fig. 5. Plan B truth table capture, versions (2_1) and (2_2)

Each behavioural version will generate a different VHDL file, thus, adapt folder names for saving them:

C:\CSD\P2\MUX_8B1\(files)

C:\CSD\P2\MUX_8B2_1\(files)

C:\CSD\P2\MUX_8B2_2\(files)

C:\CSD\P2\MUX_8B3\(files)

3. Development

Find in P2 a similar circuit designed using plan B with an architecture that corresponds to a truth table or algorithm to copy and adapt.

Translate your algorithm, flow chart or schematic into VHDL in a single file. These are up to four versions: (1) MUX_8.vhd; (2_1) MUX_8.vhd; (2_2) MUX_8.vhd; (3) MUX_8.vhd, accordingly to the plans inferred above.

The entity name and VHDL description is related to the symbol in Fig. 1 and it does not depend on the plan.

Fig. 6. The entity description in VHDL is the same for all design plans.

Start a new project in Quartus Prime, name it MUX_8_prj and select a target programmable chip (CPLD or FPGA) from our laboratory training boards. For instance, use Intel MAX II CPLD EPM2210F324C3, the same used above in plan A for better comparing circuit realisations.

Fig. 7. New project in Quartus Prime.

Synthesise your circuit and examine results. Print, analyse and comment the computer generated RTL and technology views or schematics of the circuits.

Fig. 8. Example of RTL (click to expand). Why is this circuit such different from the one in plan A Fig. 11 above?

As shown in Fig. 9, even for initial source VHDL files based on totally different plans, the same technology circuit is implemented for real in the target chip.

Fig. 9. Example of technology view. How many resources (logic cells) are used? How different is this circuit from the one represented in plan A Fig. 13 above?

Discuss advantages and drawbacks of plan A and plan B.

4. Testing

To test the solution whatever it is from any plan, use the same test bench because even if you have invented different architectures, we use always the same entity under test. The testbench fixture containing the main ideas and concepts involved in this schematic is represented in Fig. 10.

Fig. 10. Testbench VHDL schematic.

Generate from Quartus Prime the testbench template in Fig. 10. Rename it and move it to the project folder. Delete the empty process.

Translate the stimulus signals into a process and set the constant Min_Pulse in Fig. 4. This is a VHDL testbench example MUX_8_tb.vhd from which you can copy only the stimulus process and Min_Pulse constant.

Start an EDA VHDL simulator project to verify the device-under-test (DUT) using the VHDL simulator test bench.

In Fig. 11 there is an example of commented test bench results from the logic analyser (wave) available in the EDA tool simulation tool. Use coloured pens.

Fig. 13. Example of a timing diagram produced by the simulator with some mandatory comments and discussion on the way the circuit works.

5. Report

Follow this rubric for writing reports.

Lab1_2

Laboratory

Laboratory 2: designing a standard MUX_8. Flat single-file VHDL Plan A - Plan B - Prototype

[P2] MUX_DeMUX prototype using the DE10-Lite board

Lab3

[6/3]

6. Prototyping

1. Specifications

To practise with multiplexers and demultiplexers, we play with the prototype sketched in Fig. 1, a circuit MUX_DeMUX to be synthesised in a DE10-Lite board populated with an Intel MAX10 FPGA chip.

Fig. 1. MUX_DeMUX sketch.

To review the theory and how the components work, we capture a Proteus schematic and run simulation models based on classic 74LS chips: MUX_DeMUX.pdsprj. We can generate several digital signals using push-buttons, switches and even internal CLK generators. We can observe the distributed signals using an array of LED.

Fig. 2. Circuit captured in Proteus ready for simulation.

2. Planning

The complete project in Fig. 3 synthesised in the FPGA is conceived using Plan C2 and consist of three components.

MUX_4 is studied in L2.1.

DeMUX_16 is studied in L2.2.

CLK_Generator, to be studied in L8.2 with the idea of providing two additional dynamic digital signals to multiplex.

Fig. 3. Prototype plan indicating inputs, outputs and internal hierarchical architecture. On the multiplexer side, Ch2 and Ch3 will be driven by 10 Hz and 1 Hz squared signals.

3. Development

PCB. In this experiment, instead of using the board's switches and LED, we can use the DE10-Lite expansion connector represented in Fig. 4, to attach a PCB with inputs and outputs.

Fig. 4. DE10-Lite expansion connector.

Thus, once the hardware circuit for the PCB is conceived, we organise a KiCad project CSD_LAB2_PCB_v1.zip. The schematic can be captured as shown in Fig. 5. Each component contains the symbol, the footprint, and a link to the datasheet to prepare the bill of materials (BOM) spreadsheet.

Fig. 5. Schematic captured in KiCad.

The accompaning PCB component placement is shown in Fig 6.

Fig. 6. PCB layout silkscreen that shows component placement and references.

Finally, a 3D view shows the real dimensions and how the PCB will look like once soldered. If a given component fooprint 3D model is missing, KiCad works perfectly well with FreeCAD.

NOTE: In this PCB v1, components and footprints are chosen to generate a simple PCB easy to solder in our introductory course.

Fig. 7. PCB 3D representation.

As an example, the green TX LED 3D model is imported into FreeCAD from the component distributor's datasheet. The pins are cut before attaching the footprint and exporting its step model. Current CSD and DEE KiCad symbols, footprints and 3D tuned components are available in these three libraries 3dmodels.zip, footprints.zip, symbols.zip, to be unzipped for instance in the user directory.

Fig. 8. KiCad custom libraries.

FPGA circuit. Once the board is manufactured we can configure and program the FPGA using Quartus Prime.

MUX_4.vhd is solved using plan A and the equation PoS. DeMUX_16.vhd is translated as plan B. The CLK generator (CLK_Generator.vhd, T_FF.vhd, freq_div_2500000.vhd, freq_div_10.vhd) and the top application MUX_DeMUX.vhd are designed using plan C2.

The pin assignment file to be imported to the project is MUX_DeMUX_prj.csv. (update)

Fig. 9. Synthesised RTL.

FPGA MUX_DeMUX.sof (update) configuration file to be used by the Quartus Prime programmer.

Fig. 10. Quartus Prime programmer configuring the FPGA for this application.

4. Test

The final board prototype is represented in Fig. 11.

Fig. 11. Prototype connecting the inputs and outputs board to the DE10-Lite training board.

The final board prototype is represented in Fig. 12.

Fig. 12. Prototype connecting the inputs and outputs board to the DE10-Lite training board.

Laboratory measurements using the compact VB8012 instrument when selecting the Ch2 10 Hz square signal.

Fig. 13. Measurements must be like in ModelSim

We can leave ope the jumper J_T1 and connect the MUX output TX to the DeMUX input RX using a transmission line and perform measurements. The two devices can also be connected using an optical fiber or IR pair (LED, photodiode).