UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Lab 1.2

Laboratory

Laboratory 2: designing a standard MUX_8. Flat single-file VHDL: Plan A - Plan B

[P2]Demonstration prototype on standard logic circuits: MUX-DeMUX circuit

Lab 3

[30 Sept]

This is the post lab assignment PLA2_3. 

1.7.2. 2. Multiplexer or data selector design examples

Project tutorial #1: Design a MUX_8 using plan A.

This is another similar circuit to study and practise: Hex_7seg_decoder.

 

Project tutorial #2: Design a MUX_8 using plan B.

This is another similar circuit Hex_7seg_decoder.

 

1.7.3.5. Demonstration prototype MUX-DeMUX

Lab1_2

Laboratory 2 demonstration

Designing a MUX_DeMUX prototype using the DE10-Lite board

     Lab 3
Prototype specifications Planning Development Test & measurements

This is an example of next steps in the VHDL design flow: Choose an FPGA prototyping platform, design an extension PCB board to place the required inputs and outputs, assign pins, configure the chip, run and perform measurements using laboratory instrumentation.

To practise with multiplexers and demultiplexers, we imagine the prototype sketched in Fig. 1, a circuit MUX_DeMUX to be synthesised in a DE10-Lite board populated with an Intel MAX10 FPGA chip.

MUX and DEMUX

Fig. 1. MUX_DeMUX initial sketch.

To review the theory and how the components work, we capture a Proteus schematic and run simulation models based on classic 74LS chips: "MUX_DeMUX.pdsprj". We can generate several digital signals using push-buttons, switches and even internal CLK generators. We can observe the distributed signals using an array of LED.

MUX_DeMUX system

Fig. 2. Circuit captured in Proteus ready for simulation.

 

Prototype specifications Planning Development Test & measurements

We will synthesise all the logic circuits in the target FPGA Intel MAX10 10M50DAF484C7 populating the DE10-Lite board. We can conceive the project hierarchically using Plan C2 in three levels: the standard MUX_4 and DeMUX_16 components from our libraries, the component MUX_DeMUX and the MUX_DeMUX_top including the CLK_Generator to generate a pair of channels with dynamic signals. The idea is represented in Fig. 3.

MUX_DeMUX project idea

Fig. 3. Prototype plan indicating inputs, outputs and internal hierarchical architecture. On the MUX_4 side, Ch2 and Ch3 will be driven by 10 Hz and 1 Hz squared signals.

Components:

- MUX_4 is studied in L2.1.

- DeMUX_16 is studied in L2.2.

- CLK_Generator, to be studied in L8.2 with the idea of providing two additional dynamic digital signals to multiplex.

For simulating the circuit using a ModelSim testbench, Fig. 3 is convenient. For designing the hardware prototype, TX and RX are going to be external pins to characterise the signals using laboratory instrumentation.

 

Prototype specifications Planning Development Test & measurements

Printed circuit board (PCB)

In this experiment, instead of using the board's switches and LED, we can use the DE10-Lite expansion connector represented in Fig. 4, to attach a PCB with inputs and outputs. In blue colour the FPGA pins, in green colour the circuit signals.

DE10 Lite expansion connector assignments

Fig. 4. DE10-Lite expansion connector assignments.

Thus, once the hardware circuit for the PCB is conceived, we organise a KiCad project "CSD_LAB2_PCB_v1.zip". The schematic can be captured as shown in Fig. 5. Each component contains the symbol, the footprint along with its 3D model, and a link to the datasheet to prepare the bill of materials (BOM) spreadsheet.

Schematic_KiCad

Fig. 5. Schematic captured in KiCad. We can have the same schematic annotated with different versions of component footprints and thus generate several PCB.

The accompanying PCB component placement is shown in Fig 6.

Silkscreen PCB

Fig. 6. PCB layout silkscreen that shows component placement and references.

Finally, a 3D view of this PCB v1 shows the real dimensions and how the PCB will look like once soldered. If a given component footprint 3D model is missing, KiCad works perfectly well with FreeCAD to add it to the components database. 

3D PCD representation

Fig. 7. PCB 3D representation.

As an example, the green TX LED 3D model is imported into FreeCAD from the component distributor's datasheet. The pins are cut before attaching the footprint and exporting its step model.

NOTE: Our current CSD and DEE KiCad symbols, footprints and 3D components are available in these three libraries "DEE_libraries.zip" to be unzipped and saved using these KiCad installation instructions. Basically, in this introductory PCB design level, the idea behind tuning components is to enlarge their pads for easy soldering.

Custom libraries location

Fig. 8. Our DEE KiCad custom libraries.

 

FPGA circuit

Once the board is manufactured we can configure and program the FPGA using Quartus Prime translating into VHDL the schematics in Fig. 3. For instance:

"MUX_4.vhd" is solved using plan A using the equation PoS as architecture. "DeMUX_16.vhd" is translated as plan B. The CLK generator ("CLK_Generator.vhd", "T_FF.vhd",  "freq_div_2500000.vhd", "freq_div_10.vhd") and the the application "MUX_DeMUX.vhd" are designed using using plan C2. The top circuit for running ModelSim where TX = RX connected internally is "MUX_DeMUX_top.vhd".

RTL_View

Fig. 9. Synthesised top RTL for the ModelSim simulation.

ModelSim simulation:

We have to sketch a testbench and make it ready for translation into VHDL. We will use the Quartus Prime testbench template generator to instantiate it. And then, we will add some stimulus signal processes to drive the multiplexer channels and channel selector.

Fig. 10. Testbench fixture to perform simulations.

Using for instance this testbench "MUX_DeMUX_top_tb.vhd" you can perform simulations as shown in Fig. 11. 

Testbench simulations

Fig. 11. Synthesised top RTL for the ModelSim simulation.

FPGA programming and using the prototype:

The same top circuit for configuring the prototype where TX and RX are also external pins is "MUX_DeMUX_top.vhd".

RTL for prototyping

Fig. 12. Synthesised top RTL for the prototype.

Using the pin assignment tool as shown in Fig. 13, we can fill in all the spreadsheet and save it for later use in standard format. This is the pin assignment file "MUX_DeMUX_prj.csv" that can be included in the project.

Pin assignment

Fig. 13. Pin assignment spreadsheet.

This is the list of VHDL files to synthesise this project: "MUX_DeMUX_top.zip".

Using the Quartus Prime programmer tool as shown in Fig. 14 we configure the FPGA in a single step. This is the file "MUX_DeMUX_top.sof" that can also be used with the programmer alone.

Using the programmer

Fig. 14.  Quartus Prime programmer configuring the FPGA for this application.

In case we like to write the configuration flash memory (CFM) of the FPGA and make the circuit permanent, the programmer object file (.pof) is required: "MUX_DeMUX_top.pof". During internal configuration, for instance on power ON, MAX 10 devices load the configuration RAM (CRAM) with configuration data from the CFM.

Programming the FPGA configuration EPROM

Fig. 15.  Quartus Prime programmer writing the flash memory (CFM) of the FPGA  for this application.

NOTE: The initial DE10-Lite default circuit can be reinstalled using this: "DE10_LITE_Default.pof".

 

Prototype specifications Planning Development Test & measurements

The final board prototype is represented in Fig. 16.

Picture of the prototype operating

Fig. 16. Prototype connecting the inputs and outputs board to the DE10-Lite training board.

Setup the VB8012 instrument. Install the Waveforms driver and get used to the instrument.

Measurement setup using the compact VB8012 instrument. 

Let us apply in T_Ch0 a 2 MHz square waveform and acquire all the signals of interest: Analogue and digital versions of T_Ch0 and R_Ch15; digital signals TX and RX. 

Measurements using laboratory instruments

Fig. 17. Connecting analogue and digital probes from the compact instrument.
Captured waveforms

Fig. 18. Captured waveforms where we can measure the propagation delays among the several circuits stages using time cursors. Unfiltered analogue signals show ringing and coupled noise.

1) We can leave open the jumper J_T1 and connect the MUX_4 output TX to the DeMUX_16 input RX using a transmission line and perform measurements.

MUX_4

Fig. 19. MUX_4 section propagation delay from T_Ch0 to TX.

 

Wire delay

Fig. 20. The propagation delay from TX to RX using a short (1 cm) jumper is 1 ns. Well, difficult to say because the current resolution of the instrument is precisely 1 ns (1 GS/s), thus, this measurement may be wrong. A good reason for using instrumentation with more resolution, for instance the model VB-8054 offers 2 GS/s. The same measurement using a long (3 m) twisted pair wire is 15 ns.

The maximum frequency of operation (in this case the applied T_Ch0 frequency) can be calculated from the measurement of the circuit total delay as in Fig. 20. fMAX < 1/(2·tP) =  20.8 MHz. You can discuss how different are these real measurements from the calculations using gate-level simulations in ModelSim. What may be the effect of the instruments bandwidth, sampling frequency and probes, PCB component placement, long flat cable from the DE10-Lite expansion connector to the PCB, etc.?

Full delay measurement

Fig. 21. Propagation delay from T_Ch0 to R_Ch15 is 24 ns. 

Other measurements of interest:

2) The two devices can also be connected using an optical fiber or IR pair (LED, photodiode).