UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 2 problems

      - D2.4 -

 Designing a pattern detector (FSM)




1. Specifications

Our aim is to implement a circuit to detect the binary pattern "0110" received from a radio transmitter bit stream at input T. Fig. 1 shows the symbol of this pattern_detector circuit.

When the sequence "0110" is detected output Z goes high for one CLK period. Two or more adjacent patterns can also be detected as in this bit stream sequence: "01101101101..."

To make it simpler that the next version, we will assume:

- The bitstream incoming frequency is the same of the pattern_detector CLK.

- The bit stream signal is delayed half period with respect the CLK, to be able to sample stable data every CLK rising edge.

-- Transmission is continuous.


Fig. 1. Symbol.

The best way to start, is to try imagining how the output will be for a given bitstream, as represented in Fig. 2.

timing diagram

Fig. 2. Example of timing diagram.

To translate such waveforms into a testbench process for driving T, it is necessary to rely on the constant CLK_Period for both, generating the initial delay and implementing the bit sequence.

Example T testbench

Fig. 3. Example of the T process generation.

Some questions to kick off the project and organise it in four phases:

a) Draw a state diagram for the circuit's FSM. Fig. 4 shows an example.

State diagram

Fig. 4. Example of state diagram. States in this application represent the "memory", this is how many bits of the sequence are known at a given time. Five states are required, and we will assume that a CD pulse inicialises the circuit to the state zero_bits where not a single bit of the pattern is yet known.

b) Apply the FSM architecture to this project.

c) How many D_FF will contain this circuit if the states are encoded in onehot?  Draw the FSM state register.

d) Write the truth table of CC1 and CC2 and their equivalent behavioural interpretations using flowcharts.

e) Write the FSM VHDL file. Develop the circuit for an Intel Cyclone IV target chip using EDA tools. Inspect the RTL and technology views. How many D_FF registers are used in this application?

f) What is the maximum transmitter CLK if a Cyclone IV FPGA is used as the target chip to implement the prototype?