Digital Circuits and Systems - Circuits i Sistemes Digitals (CSD) - EETAC


Chapter 2 problems	- D2.18 -	Up counter BCD modulo 60 (seconds counter)	Problems	D2.17	D2.19

1. Specifications

Our goal is to design an minute or seconds counter to be used in a real-time clock device. Fig. 1 represents the symbol and function table. It is for counting using BCD code from 00 up to 59.

Fig 1. Symbol for the proposed entity.

Let us use our plan C2 to build this Counter_BCD_mod60 chaining and truncating Counter_mod16 blocks.

CLK signal. Design a CLK generator to implement a 12.5 kHz squared waveform from a 50 MHz crystal oscillator.

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Chapter 2 problems

- D2.18 -

Up counter BCD modulo 60 (seconds counter)