UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 1 problems

      - D1.1 -

Wind compass

Problems

 

D1.2

1. Specifications

We want to design a digital wind direction meter (wind_compass) as shown in Fig. 1, based on a 16-position optoelectronic rotary encoder.

To promote class and cooperative group discussions, we can plan the project in several ways, as represented in our CSD design flowchart. Each plan means a different project and circuit realisation that is useful for comparing solutions:

- Plan A: Structural (flat design with a single VHDL file), using logic equations in a canonical or simplified version.

- Plan B: Behavioural (flat design with a single VHDL file), using high-level description of the specifications.

- Plan C2: Structural (hierarchical design with multiple VHDL files), building the project using an architecture consisting of components and signals.

Symbol

Fig. 1. Circuit symbol and its realisation in Proteus wind_compass.pdsprj for better comprehending how does it work. The same project is proposed in A3.1 to be solved using a microcontroller.

Fig. 2 represents the wind compass subdivided in 16 directions each of which is assigned to a 4-bit Gray code.

Wind directions

Fig. 2. Wind compass describing the sixteen principal bearings used to measure wind direction and an example of commercial manufactured wind transducer.

Fig. 3 represents the sensor disk coded in Gray, which is used instead of binary radix-2 code to prevent spurious outputs from electromechanical switches. The objective is to develop the VHDL code and the final circuit to be synthesised into a target complex programmable device (CPLD) or a field programmable gate array (FPGA) chip.

Gray pattern and trnasducer details

Fig. 3. Gray code's error reduction with encoders (ref.) Adjacent codes differentiate themselves by only one bit.

Sensor

Fig. 4. Sensor codes assigning for instance the code "0000" to the NNW direction.

Write the truth table of the wind_compass. The inputs have to be ordered in this way: E, D(3..0).

Truth table

Fig. 5.Wind compass circuit and truth table.

Draw an example timing diagram showing the input stimulus and output responses. Assuming that Min_Pulse = 1.26 us, how long does it take to simulate all the circuit specifications?

Planning

Plan A: Logic equations.

Some questions to discuss plan A equations:

- Write the functions Y(7) and Y(14) canonically as a product of maxterms.

- Write the functions S(6) and S(1) canonically as a sum of minterms.

- Let us minimise the wind_compass using Minilog and obtain the equation output formats for SoP and PoS.

- Write the functions S(2) and Y(13) as an SoP and draw the equivalent logic circuit.

- Write the functions S(0) and Y(11) as a PoS and draw the equivalent logic circuit.

- Write the functions S(4) and Y(5) using only NOR.

- Write the functions S(3) and Y(10) using only NAND.

 

Write the VHDL code for the wind_compass to obtain the wind_compass.vhd circuit file. Project location:

C:\CSD\P2\wind_compassA\(files)

Plan B: behavioural, high-level description.

To discuss plan B, draw a schematic to translate the wind_compass truth table to VHDL, representing the required signals to interface the truth table artefact.

Write the VHDL code for the wind_compass to obtain the wind_compass.vhd circuit file. Project location:

C:\CSD\P2\wind_compassB\(files)

 

Plan C2: Hiearchical circuits based on components and signals.

Fig. 6 shows an example of an internal electronic schematic for the wind_compass when plan C2 is used. It is available for experimentation wind_compass.pdsprj. The output of Chip1 (Gray_bin_converter) is connected to both Chip2, a 1-digit 7-segment decoder (HEX_7seg_decoder), and Chip 3, a 16-bit decoder (Dec_4_16) with one-hot output to light a wheel of 16 LED to display the wind direction.

Ciircuit plan C2

Fig. 6. Internal design for the project wind_compass based on plan C2. The picture shows Gray code "1101" that is "1001" in binary representing the wind direction South-East "SE". In the way it is connected, the code "0000" corresponds to the direction "NNW", and it advances counter-clockwise up to the code "1111"which is the direction "N".

Run the Proteus simulator of the circuit in Fig. 6 . Print the screen results when you input the Gray code "0101" and explain how it works.

Design the project wind_compass using a multiple-file hierarchical approach. project location:

 C:\CSD\P3\wind_compass\(files)

Fig. 7 shows the Chip1 truth table. Realise how the 16 input combinations do not have to be ordered necessarily in binary sequential. 

Truth table

Fig. 7. Chip1 Gray_bin_converter truth table to be written to minilog for extracting equations.

 

Developing

Synthesise the projects for the given target CPLD/FPGA chip using EDA tools from Intel. Discuss using handwritten comments the RTL and the technology schematics. How many logic elements are used?

 

Testing

Test your projects functionally using the same VHDL test bench, for instance, derived from the timing diagram in specifications. Print the logic analyser timing diagrams and explain them using handwritten comments.

Perform a gate-level simulation to measure propagation delays in a given signal transition.

Deduce the worst-case propagation delay running the timing analiser tool and calculate the encoder's maximum frequency of operation for the target chip used in the design.