UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL


Enc_10_4 plan C2: hierarchical multiple-file VHDL


Binary encoder from 10 inputs to 4 outputs (type 74LS148)


Design a binary encoder 10 to 4 (Enc_10_4) with priority-high following plan C2 based on using a hierarchical structure based on components of the same kind. Data inputs D_L(9..0) are active-low, enable input (Ei_L) is also active-low. Code outputs Y(3..0) are active high, and group select (GS_L) and enable output Eo_L are active low. A similar circuit is the standard Enc_8_3 74LS148.

This is some introductory theory on encoders. Mind maps that represent main concepts involved in designing combinational circuits and our VHDL design flow that allow us to observe the same entity from diverse perspectives.

These are the circuit's symbol, truth table, and example timing diagram. rec.

Fig. 1. Enc_4_10 symbol and the way to connect keys as active-low or active-high.

Fig. 2 shows how to connect active-low keys and how to drive common anode LED from an active-low chip output.

Keys and LED
Fig. 2. How to connect keys as active-low or active-high.

Fig. 3 shows the truth table of this encoder.

Truth table
Fig. 3. The Enc_4_8 truth table.

In Fig. 4 there is an example of sketch of a timing diagram. This sketch will be translated to VHDL as stimulus to drive the testbench.

timing diagram
  Fig. 4. Example of a timing diagram showing some input activity and the predicted outputs for each time interval. When translating such sketch to a testbench is easy to check any output combination.

In Fig. 5 there is the circuit in Proteus Enc_4_10.pdsprj showing output values when clicking simultaneously key 5 and key 2 and the circuit is enabled. Pay attention to the internal design of this circuit because it is a realisation of plan C2, pretty much the same we like to implement in this project.

  Fig. 5. Example of circuit in Proteus. Run the simulation and comprehend how the truth table works and the meaning of input and output signals.


2. Planning

For the plan C2, let us to discover how to chain encoders of the same kind. And, browsing the Internet, we find the datasheet of a similar device such 74LS148 that explains what we want in its circuit application section. This are notes on the theory behind chaining encoders. They explain how to invent an Enc_8_3 using Enc_4_2 and the logic gates required to deduce the desired truth table in Fig. 3. Because this is what we are going to do: copy the same mechanism to get our Enc_10_4 as represented in Fig. 6 below, based on connecting two Enc_8_3 that were designed in another project. For instance, from P2, using plan B on the design of an Enc_10_4 or  using plan A Enc_10_4 for the same chip. Naturally, there is also a third possibilility here as explaining in the notes: use Enc_4_2 components to design the Enc_8_3 (thus, again another plan C2).

plan C2

Fig. 6. Schematic for the complete truth table using buffers to adapt inputs and ouputs to the truth table statement, that this time is based on "std_match" instruction.

 Project location:

<drive>: \CSD\P3\Enc_4_10C2\(files)


3. Development

1.- Write down the VHDL file translating the schematic in Fig. 6 above. This is an example VHDL file Enc_10_4.vhd based on Enc_8_3.vhd (plan B).

2.- Start an EDA tool project Enc_10_4_prj for a CPLD/FPGA target chip and obtain the synthesised circuit. Represent and analyse the RTL and technology views. This in Fig . 7 is an RTL view of the circuit synthesised by the computer tool.


Fig. 7. RTL generated from the VHDL synthesis looking like our sketch in Fig. 6.

3.- Examine and print a commented copy of the technology view to be very well aware of the design embedded in FPGA fabric. At this point you may like to compare such realisation with these two for the same circuit and chip: plan A, plan B.

Fig. 7.Click to enlarge. This is a technology view when targeting the FPGA chip MAX10 10M50DAF484C7.

Therefore, in some way it is not that important what plan you are using to describe your circuits, because the synthesiser knows very well what you are pretending, and it tries to synthesise the best circuit for you for a given chip (this is using default synthesis parameters). However, because each plan has its own features, not all the synthesised circuit will performance in the same way. For instance, can you analyse which one is faster encoding signals, plan A, plan B or this plan C2?


4. Testing

1.- Start an EDA VHDL simulator project and verify the Device-Under-Test (DUT) using a VHDL simulator test bench (Enc_4_10_tb.vhd), which may be exactly the same for all the different plans.

testbench Fig. 8.This is the testbench schematic. The component under test is driven by input stimulus (process) and once the simulation is completed it is possible to inspect both inputs and outputs in a logic analyser (wave).

2.- Verify applying sufficient test vectors that the device works as expected (verify the truth table). Print timing diagram screen and add comments on the signals to show how the device works.


Fig. 9.  This is an example of a functional simulation of the Unit Under Test (UUT). 


5. Report

It is required a handwritten original project report containing sections 1 - 2 - 3 - 4, scanned figures with annotations, file listings, diagrams, sketches or any other resources. Theory stuff to comprehend how the circuit works may be included in section 1 on specifications. 

When in P4, you may like to add to your report what will become section 5 on gate-level testing. How fast is this circuit (thecnology view) encoding signals?

6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works for real. The configuration file has to be downloaded into the target board as explained in the flow chart.