UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 3 problems

      - D3.4 -

Designing a pattern detector (μC - C version)

Problems

D3.3

D3.5

1. Specifications

Our aim is to implement a circuit to detect the binary pattern "0110" received from a radio transmitter bit stream at input T using a microcontroller PIC18F4520, C language and our programming style. The same circuit was already proposed as a FSM in problem: D2.4. Fig. 1 shows the symbol of this pattern_detector circuit.

When the sequence "0110" is detected output Z goes high for one CLK period. Two or more adjacent patterns can also be detected as in this bit stream sequence: "01101101101..."

To make it a simple FSM design, we will assume:

- The bitstream incoming frequency is the same of the pattern_detector CLK.

- The bit stream signal is delayed half period with respect the CLK, to be able to sample stable data every CLK rising edge.

-- Transmission is continuous.

Symbol

Fig. 1. Symbol.

The best way to start, is to try imagining how the output will be for a given bitstream, as represented in Fig. 2.

timing diagram

Fig. 2. Example of timing diagram.

Design phase #1: some questions to kick off the project and organise it as a FSM in four sections:

- Draw the hardware schematic. Buttons and switches, resistors, inputs, outputs, reset circuit MCLR_L and quartz crystal oscillator of 8 MHz. Explain how to configure inputs and outputs in init_system().

- Infer the state diagram governing the machine.

State diagram

Fig. 3. Example of state diagram. States in this application represent the "memory", this is how many bits of the sequence are known at a given time. Five states are required, and we will assume that a CD pulse inicialises the circuit to the state zero_bits where not a single bit of the pattern is yet known.

-  Draw the hardware/software diagram indicating the required RAM variables and how the FSM is solved in software.

- Draw the truth tables and their equivalent flowcharts for state_logic() and output_logic() functions.

- What is the interrupt service routine ISR() used in this application? Draw its flowchart.

- Develop and test (debugging) the project capturing the hardware circuit in Proteus and writting the C source code.

 

Design phase #2: LCD

 

Design phase #2: TMR2 to replace external CLK interrupts.