UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

PLA1_1

Q&A

PLA1_2: Circuit analysis using VHDL tools (method III)

PLA2

Lab1_2
NOTE: This post-lab assignment must be solved only after having completed successfully lab session Lab1_2 because you will copy and adapt materials and proceedings from it.
NOTE: ONLY when Lab1_2 tutorial is working in your computer, apply the following step by step tactical approach:

Step #1:
- Copy Circuit_W.vhd from our tutorial renaming it for instance Circuit_U.vhd and saving it in the given project directory:  C:\CSD\P1\Circuit_U\VHDL

- Run the complete synthesis and verification projects. Select the given target chip, start a synthesis project, synthesise the circuit, display the RTL and technology views, generate the testbench skeleton, add stimulus signals and the constant Min_Pulse, and run ModelSim functional simulations to check that wave diagrams are as expected. Check that you have configured the ModelSim colour scheme.

Step #2:
- Adapt the circuit's entity port names and equation in Circuit_U.vhd. Add only one gate from your circuit, for example:

U <= not(not(X1) or X0));

- Re-synthesise, and re-run  until you get results.
- Add a few new gates and repeat until completing the analysis. 

Specifications

Solve the circuit using method III and check results using methods II or method IV, the one that you did not use in the previous PLA1_1. Use the options indicated by your instructor.

Example of individual assignments
  Project number Circuit entity Target chip Method for checking results Proteus libraries
Student 1 A1.7 Circuit_R MAX II 4  
Student 2 A1.8 Circuit_Z Cyclone IV 2 CMOS
Student 3 A1.9 Circuit_Y MAX 10 4  
Student 4 A1.7 Circuit_R Cyclone IV 2 LS-TTL
... ... ... ... ... ...

Follow this rubric for writing reports. Because two complete projects are solved, this assignment will be is at least eight sheets of paper long report.