UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

PLA1_1

Q&A

PLA1_2: Circuit analysis using VHDL tools

PLA2

Lab1_2
NOTE: This post-lab assignment must be solved only after having completed successfully lab session Lab1_2 because you will copy and adapt materials and proceedings from it.
NOTE: ONLY when Lab1_2 tutorial is working in your computer, apply step by step tactical approach. In this PLA1_2 it means:
Step #1:
- Copy Circuit_W.vhd from Lab1_2 tutorial, renaming it for instance Circuit_L.vhd and saving it in the given project directory:  C:\CSD\P1\PLA1_2\Circuit_L\VHDL\(files)
- Select the given target chip, start a synthesis project, generate RTL and technology views, generate the testbench skeleton, add stimulus signals and constant Min_Pulse, and run ModelSim functional simulations to check that wave diagrams are OK: the same diagram that you had in Lab1_2. Check that you obtain as well the correct ModelSim colour scheme.

Step #2:
- Adapt the circuit's entity port names and equation in Circuit_L.vhd. Add only one gate from your circuit, for example:

L <= not(not(X1) or X0));

- Re-synthesise, and re-run  until you get results.
- Add a few new gates and repeat until completing the analysis. 

1. Specifications (Circuit_L)

The aim of this post-lab exercise is to analyse Circuit_L to obtain its truth table using VHDL EDA tools (method IV). PLA adapted from problem A1.1.

Circuit_L

Fig. 1. Symbol and internal architecture of Circuit_L.

Project location for saving documentation:

 C:\CSD\P1\PLA1_2\Circuit_L\VHDL\(files)

For completing the learning of all these tools, test your results using the method that you did not use in PLA_1_1, for instance, if you are testing results using method II your project location is: C:\CSD\P1\LAB1_2\PLA1_1\Circuit_L\Wolfram\(files)

1. Specifications (Circuit_M)

The aim of this post-lab exercise is to analyse Circuit_M to obtain its truth table using VHDL EDA tools (method IV). PLA adapted from problem A1.4.

Circuit_M

Fig. 1. Symbol and internal architecture of Circuit_M.

Project location for saving documentation:

C:\CSD\P1\PLA1_2\Circuit_M\VHDL\(files)

For completing the learning of all these tools, test your results using the method that you did not use in PLA_1_1, for instance, if you are testing results using method I your project location is: C:\CSD\P1\LAB1_2\PLA1_1\Circuit_M\Proteus\(files)

1. Specifications (Circuit_N)

The aim of this post-lab exercise is to analyse Circuit_N to obtain its truth table using VHDL EDA tools (method IV). PLA adapted from problem A1.5.

Circuit_N

Fig. 1. Symbol and internal architecture of Circuit_N.

Project location for saving documentation:

C:\CSD\P1\PLA1_2\VHDL\Circuit_N\(files)

For completing the learning of all these tools, test your results using the method that you did not use in PLA_1_1, for instance, if you are testing results using method II your project location is: C:\CSD\P1\LAB1_2\PLA1_1\Circuit_N\Wolfram\(files)

 

Students will be assigned as test project the one not used in PLA_1_1 (method I - CMOS, or method I - TTL-LS or method II). In this way, after having completed PLA1_2 students will be able to apply all four analysis methods.

Example of individual assignments
  Circuit Target chip Test project
Est. 1 Circuit_M MAX II  
Est. 2 Circuit_N Cyclone IV  
Est. 3 Circuit_L MAX 10  
Est. 4 Circuit_M Cyclone IV  
··· ··· ··· ....