P1 phase A: analysis of simple circuits based on logic gates 
Resources in lectures and labs:  L1.1, Lab1.1, Lab1.2  Project  objectives 

Highlighted analysis project: Circuit_C
1. Specifications (What do I have to do?)
Objective phase A: analysis. Deduce the truth table of circuit in Fig. 1 using the methods stated in this concept map (Visio). Objective phase B: design discussed in this complementary P1 design page.
Fig. 1. Example Circuit_C to analyse. C = f(D1, D0, A, B) 

Other analised circuits based on logic gates: Circuit_K, Circuits P, Circuit Q, Circuit_TV
2. Planning (How to solve it?)
Planning means organising and discussing how to proceed to reach solutions. A flow chart of sequential operations will be convenient to explain what to do, how to do it and when.
Section A: Analysis: Deduce the circuit's truth table using four approaches and compare solutions. Remember that the truth table must be verified (with other students, with different tools, etc.) before to proceed with objective B.
Fig. 2. Proposed analysis methods (Visio). 
Place your projects in different folders and name them accordingly. Normaly we use our "C:\" computer hard disk. For instance:
C:\CSD\P1\Circuit_C\Proteus\Circuit_C.pdsprj (the circuit captured in Proteus to be simulated)
C:\CSD\P1\Circuit_C\Wolfram\Circuit_C.txt (logic equations compatible with WolframAlpha engine)
C:\CSD\P1\Circuit_C\Algebra\Circuit_C.jpg, circuit_C.pdf, etc. (pictures, scanned sheets of paper, ...)
C:\CSD\P1\Circuit_C\VHDL\Circuit_C.vhd, Circuit_C_tb.vhd (the VHDL files for running the EDA tools)
And the fundamental flow for designing circuits once the initial specifications are set is always as represented in Fig. 4:

Fig. 3. Organise your project following this sequence. 
Note: In CSD do not start a project or a simulation from scratch but copying and adapting a similar exercise or file from this web. Our web contains many examples and exercises to be used as study materials and as templates to copy and adapt for other related projects.
3. Development (Let us follow the plan to obtain results)
Developing means executing a given plan to achieve a circuit solution.
Section A: Analysis: The way to proceed and the necessary CAD/EDA tools will depend on the path you follow. For example:
Method I. Circuit simulator: Draw/capture the circuit schematic in Proteus and run a simulation. Try all the possible input combinations to complete the truth table. Use files to copy and adapt them from Lab 1.1. This is an example of Proteus capture for Circuit_C.pdsprj
Method II. Numerical engine WolframAlpha: Write the circuit equation in a text file. Use files to copy and adapt them from Lab 1.1. This is an example equation Circuit_C_equation.txt to be pasted in WolframAlpha window. Do not forget to reorder input variables if such is the case before annotating maxterms and minterms and drawing the truth table.
Fig. 4. Circuit and equation at the same conceptual level. Circuit equation and WolframAlpha results representing the truth table. 


Method III. Analytical method using Boole's Algebra. Pen and paper and discussion in class or in cooperative groups.
Notes on the handwritten analysis of Circuit_C and rec.
Method IV. VHDL synthesis and simulation project: Write a VHDL file consisting of entity and architecture based on algebraic equations. for example: Circuit_C.vhd. Start a VHDL synthesis project using an EDA tool and a VHDL simulation project using a testbench (for example Circuit_C_tb.vhd) to obtain the circuit's truth table.
4. Testing (Let's verify whether the results are correct)
Testing means to check or verify that the solution is correct and agrees with the initial specifications.
Section A: Analysis: The best way to check the truth table is by comparison with the truth table obtained by other methods.
5. Report
Project report: sheets of paper, scanned figures, file listings, notes or any other resources.
6. Prototyping
Use training boards and perform laboratory measurements to verify how the circuit works. We'll explain this final design step in P3.