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## Project P1 on simple circuits using logic gates

P2

Analysis and design, truth tables, circuits, logic gates, equations, etc.

1.Specifications (What do I have to do?)

Objective 1: analysis.- Deduce a truth table of the circuits in Fig. 1 following the four methods stated in this general plan of the project (pdf) (Visio). Firstly, solve completely the Circuit_C. Secondly, repeat for the Circuit_K if you like to reach a deeper comprehension of the concepts.  Fig. 1. Example Circuit_C and Circuit_K to analyse.

C = f1(D1, D0, A, B)                                    K = f2(D1, D0, A, B)

Objective 2: design.- Synthesise different circuits using gates that comply with the truth table found above, for instance:

- Circuit_1 - Using the minimised equations from minilog.exe (a Karnaugh map computer application) C = SoP (Sum of Products) ; K = PoS (Product of Sums)

- Circuit_2 - Using the minimised equations from minilog C = PoS ; K = SoP

- Circuit_3 - Using canonical equations (C = maxterms ; K = minterns).

- Circuit_4 - Transform the Circuit_2 and build another version (using  C = only NAND gates ;  K = only NOR gates.

- Circuit_5 - Transform the Circuit_3 and build another version (using C = only NOR gates ;  K = only NAND gates.

Learning materials

Analysis:

• LAB#1: Tutorial on solving a cirucit using the method #1. Capture the circuit in Proteus and simulate.

• LAB#1: Tutorial on solving a cirucit using the method #2. Capture the circuit equations in WolframAlpha.

• To analyse the circuits use software EDA tools like:

- Proteus ISIS virtual laboratory simulator (tutorial).

- WolframAlpha computation engine (tutorial).

- VHDL EDA tools.

Design:

• LAB#2: Tutorial on solving a circui using the method #4. Capture the circuit in VHDL, sinthesise nd simulate.

• To implement the different circuits use software EDA tools like:

- Minilog.exe application to simplify truth tables (tutorial).

- VHDL EDA tools.

Basic theory:

• Some concepts on logic gates are described in this lesson on electrical characteristics.

• Tutorial: Analysis of a circuit and design of an equivalent one based on canonical expressions. The Wikipedia entry for canonical forms.

• Tutorial: Analysis of a circuit and design of an equivalent one based on SoP or PoS.

• Designing a circuit using any kind of logic equations.

• Some notes on how to design circuits using only NAND or only NOR gates.

2. Planning

Planning means organising and discussing how to proceed to achive solutions.

Plan for analysing a circuit (1), (Visio):  Let's do the same exercise (this is obtaining the circuit's truth table) using four different approaches and compare solutions.  Remember that the truth table must be verified (with other students, with different tools, etc.) before to proceed with Section B.

Place each exercise in a different folder and name them accordingly. Normaly we use as a hard disk drive our network SMB <drive> =  L:\ (available through the repositori de fitxers at the virtual desktop computer). For instance:

<drive>:\CSD\P1\Proteus\Circuit_C.pdsprj (the circuit captured in Proteus to  be simulated)

<drive>:\CSD\P1\Wolfram\Circuit_C.txt  (logic equations compatible with WolframAlpha engine)

<drive>:\CSD\P1\Algebra\circuit_C.jpg, circuit_C.pdf, etc. (pictures, scanned sheets of paper, ...)

<drive>:\CSD\P1\VHDL\Circuit_C.vhd, Circuit_C_tb.vhd  (the VHDL files for running the EDA tools)

Furthermore, something very important: do not start a project or a simulation from scratch but copying and adapting a similar exercise or file from this web. Our web contains many examples and exercises that can be used as templates ready to copy and adapt.

Plan for designing circuits (2): Once you have the truth table, you can develop/invent/create/synthesise/infer and test/check/verify several circuits from the specifications above.

3. Development (Let's follow the plan to obtain results)

Developing means doing it, executing a given plan to achieve a solution.

Analysis:   The way to proceed and the necessary CAD/EDA tools will depend on the path you follow. For example:

Method #1.- Circuit simulator: Draw/capture  the circuit schematic in Proteus and run a simulation. Try all the possible input combinations to complete the truth table.

Method #2.- Numerical engine: Write the circuit equations in a text file. Copy and paste them in WolframAlpha and run the engine to obtain the circuit's truth tables or schematics (remember that they have to be interpreted correctly because the inputs variables may be disordered). For example, this file contains some WolframAlpha equations.

Method #3.- Analytical method using Boole's Algebra. Pen and paper and discussion in class or in cooperative groups.

Method #4.- VHDL project: Write a VHDL file consisting of an entity and the architecture using the algebraic equations. Start a VHDL synthesis project using an EDA tool and simulate to obtain circuits and truth tables.

Design:   The way to invent several circuits derived form the same initial truth table will require different tools and techniques. Thus apply them conveniently to obtain results: canonical equations (sum of minterms or product of maxterms) which are the exact representation of the truth tables, minilog (or logic friday) application to obtain minimised equations (SoP, PoS), only-NOR transformation, only-NAND transformation, etc.

4. Testing (Let's see if the results are correct)

Testing means to check or verify that the solution is correct and agrees with the initial specifications.

Analysis: The best way to check the truth table is by comparison with the truth table obtained by other methods.  Another way is comparing solutions with your team mates.

For example, look at this example of solving the Circuit_K by the method #4 (VHDL synthesis and simulation): Write the circuit equations, translated them to a VHDL file, run the synthesis process, run the simulation of a VHDL test bench, get the truth table interpreting the output timing diagram from the simulator. Compare the truth table solution with others methods. This is an example testbench file. Fig. 2 shows how to fill in the truth table inspecting the timing diagram once all the combinations are simulated. Fig. 2. Example of a simulation using VHDL tools of the Circuit_K (method #4). Testing all the combinations means obtaining the truth table of the circuit as it was done using the method #1 in  Proteus.

Design: If you have developed a circuit, such as Circuit_1 based on SoP from the initial truth table, a valid way  to test it is by using any method to analyse it and deduce its truth table.

5. Report

Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources.

This is a complete example report docx pdf for the Circuit_K solved using the method #4.

6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works

Other similar projects

Other materials of interest

- Suggested problems on basic Boole's Algebra and logic gates: Problems P1.5. Problems P1.1, P1.2, P1.3. Print them form our draft collection. Work preferably in group and annotate your questions for the next session discussion in class, lab time or in office.

- Q & A. Typical questions related to this P1 project.

- You can read books on the subject or browse the Internet searching the basic theory on digital electronics. For instance, here there is a series of 14 introductory videos to our subject (Dunn, K., Bluegrass Community and Technical College). Some of the videos also include "pdf" notes and exercises and additional web references.

- Another set of online tutorials on electronics. You can use them to clarify concepts or go for a deeper comprehension of many topics covered in CSD (and in other subjects as well).