upc eetac_1


Project P1 on simple circuits using logic gates


Analysis and design, truth tables, circuits, logic gates, equations, etc.


Section A.- Draw the symbol and deduce a truth table of the circuits in Fig. 1.

Circuit C

Fig. 1. Example Circuit_C and Circuit_K to analyse.

C = f1(D1, D0, A, B)                                    K = f2(D1, D0, A, B)

Section B.- Synthesise different circuits using gates that comply with the truth table found above, for instance:

- Circuit_1 - Using the minimised equations from minilog.exe (a Karnaugh map computer application) C = SoP (Sum of Products) ; K = PoS (Product of Sums)

- Circuit_2 - Using the minimised equations from minilog C = PoS ; K = SoP

- Circuit_3 - Using canonical equations (C = maxterms ; K = minterns).

- Circuit_4 - Transform the Circuit_2 and build another version (using  C = only NAND gates ;  K = only NOR gates.

- Circuit_5 - Transform the Circuit_3 and build another version (using C = only NOR gates ;  K = only NAND gates.


To implement the different circuits use software EDA tools like:

- Proteus ISIS virtual laboratory simulator (tutorial).

- WolframAlpha computation engine (tutorial).

- Minilog.exe application to simplify truth tables (tutorial).

NOTE: These units from P1 to P12 are like book chapters showing you specification and planning on the kind of projects under analysis or design. They are like tutorial guides on how to better organise your work. The specific content of each lesson is described in the planning section.  

Learning materials



2. Planning

You always have to have a sheet of paper with the plan for the exercise so that you never get lost. (pdf) (Visio)

Firstly, solve Section A of the Circuit_C. Secondly, repeat for the Circuit_K if you have time or you like to reach a deeper comprehension of the concepts. 

Section A:  Let's do the same exercise (this is obtaining the circuit's truth table) using three different approaches and compare solutions: 

Here you are examples of a convenient plan (1), (Visio). Remember that the truth table must be verified (with other students, with different tools, etc.) before to proceed with Section B).

Place each exercise in a different folder and name them accordingly. Normaly we use as a hard drisk drive our network SAMBA L:\. (available through the repositori de fitxers) For instance:

<drive>:\CSD\P1\Proteus\Circuit_C.pdsprj (the circuit captured in Proteus to  be simulated)

<drive>:\CSD\P1\Wolfram\Circuit_C.txt  (logic equations compatible with wolframAlpha engine)

<drive>:\CSD\P1\Algebra\circuit_C.jpg, circuit_C.pdf, etc. (pictures, scanned sheets of paper, ...) 

Furthermore something very important: never start a project or a simulation from scratch but copying and adapting a similar exercise or file from this web. Our web contains many examples and exercises that can be used as templates ready to copy and adapt.

Section B: This is an example plan (2). Once you have the truth table, you can develop/invent/create/synthesise/infer and test/check/verify several circuits from the specifications above.


3. Development

Section A:   The way to proceed and the necessary CAD/EDA tools will depend on the path you follow. For example:

Method 1.- Circuit simulator: Draw/capture  the circuit schematic in Proteus and run a simulation. Try all the possible input combinations to complete the truth table. 

Method 2.- Numerical engine: Write the circuit equations in a text file. Copy and paste them in WolframAlpha and run the engine to obtain the circuit's truth tables or schematics (remember that they have to be interpreted correctly because the inputs varaibles are disordered). 

Method 3.- Analytical method using Boole's Algebra. Pen and paper and discussion in class or in cooperative groups.

Method 4.- (in P2) VHDL project: Write a file in VHDL consisting of an entity and the architecture using the algebraic equations. Start a VHDL synthesis project using an EDA tool and simulate to obtain circuits and truth tables.


Section B:   The way to invent several circuits derived form the same initial truth table will require different tools and techniques. Thus apply them conveniently to obtain results (canonical equations (sum of minterms or product of maxterms) which are the exact representation of the truth tables, minilog (or logic friday) application to obtain minimised equations (SoP, PoS), only-NOR transformation, only-NAND transformation, etc.


4. Testing

Section A: The best way to check the truth table is by comparison with the truth table obtained by other methods.  Another way is comparing solutions with your team mates.

For example, look at this example of solving the Circuit_K by the method #4. (VHDL synthesis and simulation): Write the circuit equations, translated them to a VHDL file, run the synthesis process, run the simulation of a VHDL test bench, get the truth table interpreting the output timing diagram from the simulator. Compare the truth table solution with others methods. These are the files: docx pdf report, VHDL file, testbench file, WolframAlpha equations. Fig. 2 shows how to fill in the truth table inspecting the timing diagram once all the combinations are simulated.

Simulation of the Circuit_K


Fig. 2. Example of a simulation using VHDL tools of the Circuit_K. Testing all the combinations means obtaining the truth table of the circuit. 

Section B: If you have developed a circuit, such as Circuit_1 based on SoP from the initial truth table, the way to test it is using any other method to analyse it and deduce its truth table. 

5. Report

Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources


6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works


Other similar projects

- In addition to the three methods discussed in this P1 project to obtain the truth table of a simple combinational circuit, there is another one  (Method #4) which uses VHDL synthesis and simulation tools (P2). See the example here in this tutorial.

Other materials of interest

- Exams, questions, problems and projects

- Suggested problems on basic Boole’s Algebra and logic gates: Problems P1.5. Problems P1.1, P1.2, P1.3. Print them form our draft collection. Work preferably in group and annotate your questions for the next session discussion in class, lab time or in office.

- Q & A. Usual questions related to this P1 project that have been discussed in previous terms.