UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 2 problems

      - A2.5 -

 Analysis of a synchronous circuit (Circuit_F)

Problems

A2.4

A2.6


1. Specifications

The circuit represented in Fig. 1 is composed of T_FF. Let us deduce how it works by means of a timing diagram, how many states does it have and what may be its application, if any. Synchronous structures are much more simple to analyse than asynchronous circuits because all flip-flops are driven by the same and only CLK signal. Synchronous circuits will be systematically designed following our FSM approach presented in P6.

Circuit_F

Fig 1. Circuit_F symbol and internal structure.

Method I. Handwritten analysis.

Let us do it in two steps:

Step #1: to get some practice on how a flip-flop works, analyse the behaviour of a single T_FF in Fig. 2 and represent the output Q in a timing diagram like the one represented in Fig.3.

T_FF

Fig 2.  T_FF symbol, function table and state diagram.

Indicate always the T sampled values on the CLK rising edges using dots.

Waveforms

Fig 3. Example input waveforms to be used as stimulus for calculating the output Q. 

 

Step #2: the full circuit. Deduce the output Q(3..0) of the circuit represented in Fig. 1. The procedure to follow is presented in our P5 highlighted project.

Waveforms

Fig 4. Waveforms.

Discuss how many states the system is capable of memorising.

Discuss what may be the function or application of the circuit. 


Method II. Proteus capture and simulation. Components from CMOS or LS-TTL libraries.

Capture Fig. 1 in Proteus and run simulations. For instance copy and adapt a similar structure such Proteus circuit based on CMOS classic chips. When picking parts from the library to mount your circuit, do this initialisation from Proteus top menu:

 --> Tool --> Global Annotator --> Total.

Print and discuss your results adding comments on the printed waveforms from the logic analyser.


Method III. VHDL synthesis and simulation. Target chip MAXII EPM2210F324C3

Get the component T_FF model and translate to VHDL the top circuit (Circuit_F.vhd) to be able to start a new multiple-file plan C2 project.

Synthesise the project and print the RTL view. Be aware that the "number of registers" in the project's summary spreadsheet must be "4".

Prepare and use a VHDL testbench to demonstrate that the circuit's timing diagram looks like that obtained in the two previous methods.

Measure the propagation time CLK to output (tCO). Calculate the maximum CLK frequency of operation.


Optional: Design exercise

e) Design an FSM that generates the same output Q(3..0).