UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL


Adder_1bit plan B: behavioural single-file VHDL


Behavioural design of a 1-bit full adder circuit  (Plan B)

1. Specifications

Design a 1-bit adder using a behavioural description.


Fig. 1. Symbol and truth table of a 1-bit adder circuit. It is also called full adder.

This in Fig. 2 is a simple sketch that represents the truth table in time. The idea of applying input vectors that can be any binary combination.


Fig. 2. Timing diagram where all the inputs are applied sequentially and hence, the output is predicted accordingly to the truth table.


2. Planning

The VHDL file will be named Adder_1bit.vhd, the same name given to the entity. The project name is Adder_1bit_prj.

Plan B) Behavioural (flat, single-file project).

B1.- This is a plan to write the truth table.


The project location is  C:\CSD\P3\Adder_1bit_B1\(files)


3. Developing the project using EDA tools

Plan B behavioural. This is the translation to VHDL of the plan B1 above: Adder_1bit.vhd .


4. Testing and validating the design

 An example test bench Adder_1bit_tb.vhd. Run the VHDL simulation EDA tool to obtain and discuss the timing diagram.  Remember that from the testing point of view, even if you have designed the Adder_1bit using several plans, you can use all the time the same testbench.


Fig. 4. Example testbench showing results


5. Report

Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources.


6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works.