UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 1 problems

      - D1.2 -

BCD_7seg_decoder chip

Problems

D1.1

D1.3

1. Specifications

Design a BCD_7seg_decoder chip similar to the classic 74LS47 the symbol of which is represented in Fig. 1 using several plans and VHDL EDA tools (design flow). The synthesised circuit will be tested using VHDL testbenches. Discuss using handwritten comments the RTL and the technology schematics. How many logic elements are used?

BCD_7seg_Decoder

Fig.1. When operating, this decoder only deals with inputs from 0 to 9 ("0000" to "1001"). The remaining 6 combinations are of no interest.

truth table

Fig.2. Truth table definition as an incomplete circuit.

Draw an example of timing diagram to be used later as stimulus in the VHDL testbench when verifying the synthesised circuit. Consider Min_Pulse = 3.34 ms.

CPLD or FPGA target chip options:

 option #1.: MAX II

 option #2.: MAX 10

 option #3.: Cyclone IV

 

2. Planning

Plan A structural circuit based on logic gates and equations in a single VHDL file. We have many estrategies, for instance:

option #1: use minilog to obtain PoS for outputs a, b, c and d. Use minilog to obtain SoP for outputs e, f and g.

Project location:

 C:\CSD\P2\BCD_7seg_decoder\planA1\(files)

option #2: use minilog to obtain SoP for outputs a, b, c and d. Use minilog to obtain PoS for outputs e, f and g.

Project location:

 C:\CSD\P2\BCD_7seg_decoder\planA2\(files)

 

Plan B behavioural approach writing the truth table or the high-level description or algorithm in VHDL in a single VHDL file.

Project location:

 C:\CSD\P2\BCD_7seg_decoder\planB\(files)

 

Plan C2 is a hierarchical architecture based (multiple VHDL file) on components and signals.

For instance: using the method of decoders (MoD). Project location:

 C:\CSD\P2\BCD_7seg_decoder\MoD\(files)

 

After having studied P4 tutorials, additional questions can be added to our report. For instance: