UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 2 problems

     - D2.11 -

Wireless IR TV remote control




1. Specifications

We want to design a simple TV remote as shown in Fig. 1. To simplify it, only channel and volume selection. Its internal architecture is based on channel and volume code generators of 4-bit binary combinations (chip1 and chip2), a Hex_7seg_decoder (Chip3), and the IR light series Transmitter_TX (Chip4). Chip3 was solved in Chapter 1 as a combinational circuit. Chip4 will be the objective of another project, thus we focus our attention in Code_generator. that is used twice.


Fig. 1. Remote control and it suggested internal architecture.

The idea of the chip Code_generator is represented in Fig. 2, a button synchroniser Sync Chip1 that drives a standard Counter_mod16 (Chip2) up and down when buttons UP and DN (down) are pressed. Codes rotate when reaching the terminal count (15 when up and 0 when down).


Fig. 2. Proposed architecture for the chip Code_generator.

 Timing signals are represented in Fig. 3. When the user clicks a button, output CE is set high during a CLK period; output UD_L is set high for a CLK period as well but only when the button UP is sensed. Clicking a button represents incrementing or decrementing the channel count by 1.


Fig. 3. Example waveforms that show how control output signals CE and UD_L are generated depending on the buttons pressed. The key point is that one one synchronous pulse is generated even if the button is kept clicked for a long time ('long time' here in this context means many CLK periods).

Some questions to kick off the project and organise it in four sections. Apply the FSM architecture to this problem.

a) Infer and draw the Sync circuit state diagram. Annotate all the state transitions and outputs.

State diagram

Fig. 4. State diagram proposed for the Sync circuit to allow only one code generated after clicking a button. 

b) Adapt the FSM architecture to this problem, naming and connecting all signals and inputs and outputs.

c) Sketch a timing diagram showing the main operations.

d) Draw the state register if coding the machine in binary sequential. How many D_FF of memory are used in this problem?

e) Write the CC2 truth table to obtain the outputs of the circuit and its flowchart.

f) Design the CC1 truth table to obtain the next state to go and its flowchart.

g) Write the VHDL file and start an EDA project to synthesise the circuit and obtain results. Inspect the RTL and verify that it looks like your schematic. Check the number of D_FF, print and comment the schematics.

h) Get the Counter_mod16 VHDL code from its tutorial and build the complete top Code_generator project.

j) Write a VHDL test bench driving UP and DW signals and run the EDA simulation tool to verify your design.

k) The CLK frequency for this application to be able to sample buttons is 80 Hz. Design a  CLK generator to obtain such frequency from a 50 MHz crystal oscillator.

Optional. Other additional features:

- How can you implement this functionality: if you keep pressing the button the channel count goes up or down one number every second until the button is released (most commercial remotes work in this way). Thus, sequencing the 16 codes will be possible in two ways: clicking the button 16 times or instead keeping the button pressed for 16 seconds.  

- How to design the Chip3 Transmitter_TX that has the function to convert 4-bit binary codes into IR light? Designing such block is a new interesting project where you can learn about frequency, pulse width or pulse duration modulations. You can even learn about the Receiver_RX block to convert light into 4-bit binary codes.

- How to add a ON/OFF button to power up and switch off the device?