UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Lab 3

Laboratory

Lab 4.1: propagation delay and speed: Adder_1bit, Adder_16bit (RC), Adder_16bit (CLA)

Int_add_subt_8bit [P4] Arithmetic circuits and timing analyser and VHDL gate-level simulations

Lab 4.2

[14 Oct]

This is the post lab assignment PLA4

1.5.5.1. Gate-level simulation: signal propagation delay measurement

How to measure signal's propagation time for a given target chip: post-synthesis model in VHDL (VHO file and its associated SDO/SDF delay file) and gate-level VHDL simulation in ModelSim.

1.5.5.2. Timing analyser spreadsheet tool

Using the Quartus Prime timing analyser we can measure the worst-case scenario: longest propagation delay (tP) of a given circuit.

1.5.5.3. Calculating the circuit's maximum operational speed Mops (millions of operations per second).

And therefore, from the longest propagation path from input to output, we can calculate the circuit's speed as millions of operations per second (Mops).

In the lab we have some commercial CPLD and FPGA target chips where to synthesise our circuits. For instance:

  CPLD FPGA
Xilinx XC2C256-TQ144 - 7 Spartan-3E XC3S500E-FG320
Intel MAX II EPM2210F324C3 (option #1) Cyclone IV EP4CE115F29C7 (option #2)
Lattice ispMach4128V TQFP100 MachXO

NOTE: Quartus Prime does not generate delay files (sdo) for Intel MAX 10 devices, and thus we cannot practise gate-level simulations in ModelSim for this family. However we still can use the timing analyser Quartus Prime tool targeting MAX 10, MAX II and Cyclone IV FPGA.

Let us continue the Adder_1bit based on MoM from the last Lab 3 measuring propagation time of signals in a given transition and also the maximum speed of computing.

Project tutorial #1: Add the gate-level simulation to the Adder_1bit (MoM)

This tutorial shows how the circuit parameters depend on the technology in which it is synthesised.

 

1.9.1.2. n-bit adders  [L3.2]

1.9.1.2.1. Ripple-carry adder (RC): Adder_4bit, Adder_8bit [Lab 3], Adder_16bit [Lab 4.1],(option #1)

1.9.1.2.2. Carry-lookahead adder (CLA): Adder_4bit, Adder_16bit [Lab 4.1], (option #2)

Now we have in mind solving the same project Adder_16bit using two different architectures synthesised for the same target chip. Thus, learning basic concepts on designing architectures for circuit optimisation accordingly to given parameters, for instance speed or resource utilisation. You will observe differences in performance between ripple carry and carry-lookahead adders.

Project tutorial #2: Design an Adder_16bit using plan C2 and ripple-carry (RC) architecture

 

Let us complete this lab tutorial considering the enhanced architecture based on carry-lookahead (CLA) adders. You will observe what is the difference between ripple carry and carry-lookahead adders, which one is faster and why? Which one uses less resources meaning saving chip space and power consumption?

Project tutorial #3: Design an Adder_16bit using plan C2 and carry-lookahead (CLA) architecture



Conclusions

These three projects have been used for learning new tools: gate-level simulation in ModelSim and Quartus Prime timing analyser, and for demonstrating how digital technologies, gate switching (operating speed) and logic resources (logic elements) are linked. We can imagine that when more resources are used the circuit is more power demanding. You can balance speed and power consumption choosing alternative designs.