UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Lab 6

Laboratory

Laboratory 7: standard sequential devices counters and registers. Plan X,  Plan Y, Plan C2

[P7] Counter prototype. Debouncing push-buttons

Lab 9

[18 Nov]

This is the post lab assignment PLA6_7. 

2.7.3. Design plan X: state enumeration. Designing counters as FSM for small number of states and any output code. 

2.7.3.2.  Example: Counter modulo 12  as another P6 application.

Project tutorial#1: Counter_mod12 using plan X

 

2.7.4. Design plan Y: Designing large synchronous counters and registers using the VHDL arithmetic library and STD_LOGIC_VECTOR, single-file VHDL project.

2.7.4.1. Example: Counter modulo 12. Adaptable to any counter or register size

Project tutorial#2: Counter_mod12 using plan Y

 

2.7.5. Design plan C2: count truncation and count expansion [L7.3]. Concepts and chaining signals (terminal count - count enable). Hierarchical structures, standard components {Counter_mod16} and logic, VHDL multiple-file project.

2.7.5.1. Example: Counter modulo 12 and prototype experimentation

Project tutorial #3: Counter_mod12 using plan C2

 

Compare and discuss advantages and drawbacks for the same entity Counter_mod12 using these several design strategies.

From all these lessons on counters, truncation and expansion, it is not that difficult implementing for example a real-time clock HH:MM:SS or similar practical products. P8 is the unit devoted to advanced digital systems or dedicated processors.