UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL


Lectures and labs 


Chapter 1: Combinational circuits
W1 L1.1 L1.2 L1.3 L1.4 L1.5                  
W2 L1.6 L2.1 L2.2   LAB1_1   PLA1_1            
W3     L2.3 L2.4 L2.5   LAB1_2 PLA1_1 PLA1_2          
W4 L3.1 L3.2 L3.3 LAB2 PLA1_2 PLA2
W5 L4.1 L4.2 L4.3 LAB3 PLA2 PLA3
W6 LAB4 PLA3 PLA4 Q1-4



Fig. 1. Symbol of a generalised  combinational circuit. This block is described by its truth table or the equivalent canonical equations product of maxterms or sum of minterms.


P_Ch1 post lab assigments after having practised in lectures and lab sessions: 


Due date September 26

Circuit analysis using Proteus and Wolfram Alpha



October 3

Circuit analysis using VHDL tools




October 10

Circuit design using single-VHDL file plans A and B




 October 22 Circuit design using hierarchical plan C2

Q & A


Chapter 2: Sequential systems
W6 L5.1 L5.2 AR1                       
  Midterm exam
W7 L5.3   LAB5   PLA4 PLA5
W8   L5.4 L6.1 L6.2     LAB6   PLA5 PLA6        
W9     L7.1 L7.2   LAB7   PLA6 PLA7
W10 L7.3 L8.1 L8.2   PLA7


Fig. 2. Internal architecture of a synchronous canonical finite state machine as studied in CSD.

The state register contains a bank of r D_FF memory cells. r depends on state coding style.

The FSM, even if structured in three blocks,  is implemented in a single VHDL file (the only time where plan C1 is used in CSD).

P_Ch2 post lab assigments after having practised in lectures and lab sessions: 


Due date November 7

Gate-level measurements (how fast is a circuit operating?)



November 14

Analysing circuits based on 1-bit memory cells (FF)




November 21

Implementing finite state machines (FSM)




  December 3

Counters and dedicated processors

Q & A


Chapter 3: Microcontrollers
W10           LAB9     PLA9          
W11 L9.1 L9.2 L9.3      
W12 L9.4 L10.1 L10.2   LAB10 PLA9 PLA10 Q5-8
W13 L11 L12.1 L12.2      LAB11   PLA10 PLA11
W15 L12.3 AR2 AR3 LAB_AR PLA11 Q9-12

Software structure

Fig. 3. The key concept in Chapter 3 is adapting the FSM structure to software environment in C language. Our programming style and code organisation will mimic concepts studied in previous chapters.

P_Ch3 post lab assigments after having practised in lectures and lab sessions: 


Due date December 12

Basic digital I/O pins


December 12

Phase #1: Adapting FSM to μC



January 9

Phase #2: peripheral LCD. Phase #3: TMR0 time-base



Key note: PLA3, PLA7 and PLA11 are group online submissions at the Atenea platform. Only materials submitted before due dates are considered for grading. To avoid any problems with file types or sizes, please, do not wait until the last minute. And be sure that your files can be downloaded and unzipped correctly and also that there is a clear link to your video presentation. Add as well your own self-assessment indicating what grade you might get with respect to the marking grid.