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Digital Circuits and Systems (CSD)  planning

Course map

Chapter 1: Combinational circuits Week 1 Week 2 Week 3 Week 4 Week 5
      PLA#1.1 Q#1.1 PLA#1.2



Fig. 1. Symbol of a generalised  combinational circuit.  


Chapter 2: Sequential systems Week 6 Week 7 Week 8



Fig. 2. Internal architecture of a finite state machine as studied in CSD.

The state register contains a bank of r D_FF memory cells.

This FSM will be implemented in a single VHDL file.


Chapter 3: Microcontrollers Week 9 Week 10 Week 11 Week 12
  Q#2.1 Q#2.2 PLA#3.1 P_Ch3


Software structure 

  Fig. 3. Adapting the structure of a FSM to the software environment in C language. Our program structure will be very similar to the previous one studied in chapter 2.