UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL


Lectures and labs 


Chapter 1: Combinational circuits
W1 L1.1 L1.2   L1.3 L1.4   L1.5                  
W2   L1.6 L2.1     LAB1.1   L2.2     PLA1.1  
W3     L2.3 L2.4     LAB1.2   L2.5   PLA1.1 PLA1.2  
W4 L3.1 L3.2 LAB2 L3.3 PLA1.2 PLA2
W5     L4.1 L4.2     LAB3   L4.3   PLA2 PLA3  
W6   LAB4   AR1    PLA3 PLA4 Q1-4
      Midterm exam      

Fig. 1. Symbol of a generalised  combinational circuit. This block is described by its truth table or the equivalent canonical equations product of maxterms or sum of minterms.

P_Ch1 post laboratory assigments after having practised in lectures and lab sessions:
PLA1.1 Due date February 28 Circuit analysis using Proteus (method II) and Wolfram Alpha (method IV)  
  PLA1.2   March 6     Circuit analysis using VHDL tools (method III)  
PLA2 March 13 Circuit design using single-VHDL file plan A and plan B
      PLA3   March 24     Circuit design using multiple-file hierarchical plan C2  
PLA4 April 10 Gate level measurements: how fast is a circuit operating? Q & A

Chapter 2: Sequential systems
W6   L5.1 L5.2                          
W7       LAB5 L5.3   PLA5 PLA4
W8 L5.4 L6.1 LAB6 L6.2 PLA5 PLA6
W9 L7.1 L7.2 LAB7 L7.3 PLA6 PLA7
W10 L8.1 L8.2   PLA7

Fig. 2. Internal architecture of a synchronous canonical finite state machine as studied in CSD.

The state register contains a bank of r D_FF memory cells. r depends on state coding style selected.

The FSM, even if structured internally  in three blocks, is implemented in a single VHDL file with processes instead of components (the only time where plan C1 is used in CSD).

P_Ch2 post laboratory assigments after having practised in lectures and lab sessions:
PLA5   Due date April 17 Analysing circuits based on 1-bit memory cells (FF)    
  PLA6   April 24   Implementing finite state machines (FSM)    
      PLA7   May 5   Counters and dedicated processors   Q & A

Chapter 3: Microcontrollers
W10                   L9.1            
W11 L9.2 L9.3 LAB9 PLA9 Q5-8
W12 L9.4 L10.1 LAB10 L10.2 PLA10  
W13 L11 L12.1  LAB11 L12.2 PLA9 PLA11
W14 L12.3 AR2 LAB_AR AR3 PLA10 Q9-12
W15 PLA11

Final exam

Chapter 2

Chapter 3

Software structure

Fig. 3. The key concept in Chapter 3 is adapting the FSM structure to software environment in C language. Our programming style and code organisation will mimic concepts studied in previous chapters.

P_Ch3 post laboratory assigments after having practised in lectures and lab sessions:
PLA9 Due date May 15 Microcontroller. Basic digital I/O pins
  PLA10   May 22   Phase #1: Adapting FSM to μC. Interrupts    
PLA11 June 2 Phase #2: peripheral LCD. Phase #3: internal TMR Q&A

Key note: PLA3, PLA7 and PLA11 are group online submissions at the Atenea platform. Only materials submitted before due dates are considered for grading. To avoid any problems with file types or sizes, please, do not wait until the last minute. And be sure that your files can be downloaded and unzipped correctly and also that there is a clear link to your video presentation. Add as well your own self-assessment indicating what grade you might get with respect to the marking grid.