UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

 

Planning lectures and labs 

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Chapter 1: Combinational circuits
L1.1 L1.2 L2.1 L2.2 L3.1 L3.2 L4.1 L4.2
LAB1_1 LAB1_2 LAB2 LAB3 LAB4
P_Ch1 presentation SP1_1 SP1_2 SP1_3 SP1_4
P_Ch2 presentation
              Q1-4

cc

 

Fig. 1. Symbol of a generalised  combinational circuit. This block is described by its truth table or the equivalent canonical equations product of maxterms or sum of minterms.

 


Chapter 2: Sequential systems
L5.1 L5.2 L6.1 L6.2 L7.1 L7.2 L8
LAB5 LAB6 LAB7
  SP2_1 SP2_2 SP2_3
Q5-8
FSM 

Fig. 2. Internal architecture of a synchronous canonical finite state machine as studied in CSD.

The state register contains a bank of r D_FF memory cells.  r depends on state coding style.

The  FSM, even if structured in three blocks,  is implemented in a single VHDL file (the only time where plan C1 is used in CSD).


Chapter 3: Microcontrollers
L9 L10 L11 L12
LAB9 LAB10 LAB11
SP2_4 SP3_1 SP3_2 SP3_3
P_Ch3 presentation     Q9-12

Software structure 

  Fig. 3. The key concept in Chapter 3 is adapting the FSM structure to software environment in C language. Our programming style and code organisation will mimic concepts studied in previous chapters.