UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 2 problems

     - D2.14 -

Traffic light controller (version 2)




1. Specifications

This is an evolution of the Traffic light controller FSM in P6 developed as a tutorial.  


Fig 1. Street intersection to be controlled.

Fig. 2 shows its internal architecture as a dedicated processor.

Traffic light controller

Fig 1. The complete traffic light controller building blocks (Visio).

Some ideas to start this project:

- Solve the  CLK generator. Generate 4 Hz squared CLK signal from the crystal quartz oscillator available on the training board. For instance, 25.175 MHz in the Altera's UP2 (example of architecture) or 50 MHz in the Digilent NESYS 2 board. Generate the 2 Hz square signal to drive the yellow LED at night mode.

- Using this Programmable_timer generate the signals required by the traffic light. For instance: Green A = 63 s,  Yellow A = 13 s, Green B = 45 s,  Yellow B = 8 s. Reorganise your state diagram so that you can command the programmable time as well as external lamps.

- Add CA and CB sensors to stop normal operation when cars are not detected in a given street.

- Add PA and PB push-buttons to allow pedestrians to cross the intersection at any time when the traffic light sequence is locked in a given street because there are no cars in the other.  



Fig. 3. Example of traffic light waveforms. Results from the VHDL EDA simulator zooming the transition from Green_A to Yellow_A in order to demonstrate how the FSM changes states synchronously while generating both internal signals and external outputs.

Optional. Other additional features:

- Add a transmission system able to report the current state of the traffic light controller to a remote computer and to accept orders from a central system (full duplex communication).

- Add a car speed measurement system with speed limit indicators and numeric displays signs.