UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Lab 2

Laboratory

Laboratory 3: Multiple-file plan C2 structural VHDL designs: Adder_1bit, Adder_8bit

This highlighted [P3] is the reference structural hierarchical design

Lab 4.1

[7 Oct]

This is the post lab assignment PLA2_3.

1.5.2.4. Plan C2: hierarchical design multiple-file (components and signals)

Learning how to use components is the key point of the CSD course because it will allow you to invent and develop large circuits hierarchically, as you see in Proteus schematics, where you can click "Cntl+C" to enter the child sheet of each subcircuit. Thus, from now on, subcircuits will become VHDL components and wires and cables signals.

1.5.2.4.3. The method of multiplexers (L3.3)

1.9. Binary (radix-2) arithmetic circuits

1.9.1. Addition

1.9.1.1. 1-bit full adder

Project tutorial #1: Design an Adder_1bit using plan C2 and the method of multiplexers (MoM)

 

1.5.2.4. Plan C2: hierarchical design multiple-file (components and signals)

1.5.2.4.1. Circuit expansion using components of the same kind

1.9.1.2. n-bit adders

1.9.1.2.1. Ripple-carry adder: {Adder_4bit}

Project tutorial #2: Design an Adder_8bit using plan C2