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Chapter 1 problems |
- D1.7 - |
16-bit demultiplexer / 8-bit demultiplexer |
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Design a DeMUX_16 similar to the classic 74HCT154 chip in a programmable logic device (PLD) target chip.The circuit symbol and its truth table is represented in FIg. 1.
Fig. 1. DeMUX_16 symbol and truth table. Select channel input S(3..0) and outptus Ch(15..0) are defined as vectors. |
As theory, explain what kind of applications will use DeMUX, and what may be input data D.
2. Planning
Plan A using our VHDL design flow using logic equations and EDA tools for developing and testing.
Example equations are used in lecture L2.2.
Plan B capturing in VHDL the truth table or proposing the circuit algorithm as a flowchart.
An example schematic and VHDL translation is used in lecture L2.2.
Plan C2 hierarchical circuit using DeMUX_8 components.
Plan C2 hierarchical circuit using DeMUX_4 components.
Design a DeMUX_8 similar to the classic 74HCT138 chip in a programmable logic device (PLD) target chip. The circuit symbol and its truth table is represented in FIg. 1.
Fig. 1. DeMUX_8 symbol and truth table. Select channel input S(2..0) is defined as vector. |
As theory, explain what kind of applications will use DeMUX, and what may be input data D.
2. Planning
Plan A using our VHDL design flow using logic equations and EDA tools for developing and testing.
Example equations are used in lecture L2.2.
Plan B capturing in VHDL the truth table.
An example schematic and VHDL translation is used in lecture L2.2.
Plan C2 hiearchical circuit using DeMUX_4 components.