P_Ch1: 8bit 2C adder, subtractor and comparator
1. Specifications
Perform several example 2C operations (using both positive and negative integers) on the circuit in Fig. 1 to verify whether you understand how it works. Calculate as well the zero (Z), overflow (OV), and sign (S) indicators.
1. Design an 8bit adder, subtractor and comparator in two's complement with zero(Z), sign (S) and overflow (OV) flags using VHDL and a multiple file hierarchical structural approach. Discus the symbol (below in Fig 1) , the truth table and the timing diagram of this circuit. How long is the truth table?
Fig. 1. Symbol of an 8bit 2C adder/subtractor. 
2. P_Ch1. We'll discuss the way to add, substract and compare. Here you are a template for this P_Ch1: 8bit adder/subtractor/comparator. As shown in Fig. 2, the circuit in Fig. 1 is expanded with the new feature of 2C number comparison, therefore 3 additional outputs are required: GT (greater than) to detect when A > B, EQ (equal to) to detect when A = B, and LT (less than) to detect when A < B.
Fig. 2. Symbol of the project. 
3. Once the circuit works and is tested functionally as usual, perform a gatelevel simulation to determine the circuit maximum speed of operation. Below you've got some materials to study about gate delays. This is the VHDL design flow (pdf, Visio) where you see that the gatelevel simulation is the 5th design step to save time before making real measurements in the lab. For instance, two different experiments can be carried out:

Learning materials:
 Let's learn how to perform basic operations using binary number system: addition, subtraction, comparison, multiplication, etc. Explain how does work the two's complement (2C) to represent positive and negative integer numbers. Solve exercises on arithmetic operations (like in the problem 4.1 in this collection). Here you are a project solved in Proteus: 8bit 2C adder and subtractor. Run and try it to visualise better how it operates the input and output data.
 This is the tutorial on the design of an expandable 1bit comparator which can be used as a building block for the 8bit comparator (Comp_8bit) and later for the 8bit two's complement comparator (Comp_2C_8bit).
 Notes in this lesson about propagation delays, computing speed caclulations and gatelevel simulations. These pair of tutorials on the design of ones counters also include gatelevel simulations.
2. Planning
Structural design. Thus, as you've seen in P3, let's plan the following separated projects, and then combine them all:
1. Design flow steps: 1)  2)  3)  4): Study how the overflow logic (OV) works and why it is designed so (these notes can suit you). Study how the zero flag (Z) works. Is it the same as in the Adder_8bit? Design the structure of an 8bit adder/subtractor using components and signals as for example in this plan. Use any hierarchical example or tutorial project to copy and adapt to translate to VHDL and get the components from previous projects. Count and name all the VHDL files involved in the project. Name the folder to keep all the project files:
<disk>/CSD/P4/Adder_subtractor_8bit/(files)
2. Design flow steps: 1)  2)  3)  4): Design the structure of an 8bit adder/subtractor/comparator (Add_Subt_Comp_8bit) using components and signals. This is essentially, designing first the Comp_8bit and then the 8bit 2C comparator (Comp_2C_8bit) and placing it in the top schematic along with the Adder_subtractor_8bit.
<disk>/CSD/P4/Add_Subt_Comp_8bit/(files)
3. Gatelevel simulations:
Add the gatelevel simulation as the last step in the design flow. So that you can perform measurements of the circuits' speed. How many millions of operations per second (Mops) can perform the Add_Subt_Comp_8bit?
Once you have completed the planning, you can start the development of the Adder_subtractor_8bit.vhd. Write down the VHDL files using components and signals modifying a convenient seed circuit. For instance, these circuits may suit you: Adder_4bit, Adder_8bit, Adder_subtractor_8bit. You see that the 4bit and 8bit adders are slightly modified because the Z flag condition is different now in 2C arithmetic.
Run the EDA tool to synthesise the circuit. Print and comment the RTL schematic. Is it like what you had sketched in the plan?
And repeat the design process for the Add_Subt_Comp_8bit.vhd project.
4. Testing (functional simulation)
From the initial timing diagram sketch, Convert it into a VHDL testbench like in this file Adder_subtractor_8bit_tb.vhd writing the inputs activity and the Min_Pulse constant in the template produced by the EDA tool. Surely, it's going to be a good idea the adaptation of the test vectors used in the 8bit adder. Use positive and negative numbers as inputs to the circuit. Check overflow and zero situations.
Run the EDA VHDL simulator and demonstrate how the circuit works adding comments to the printed sheet of paper containing the waveforms.

Fig. 3. Example test with some input vectors. A, B and R are 2C numbers. 
And repeat for the project 8bit adder subtractor comparator.
5. Testing (gatelevel simulation)
Run a gatelevel simulation to measure the worst case delay and the maximum speed of operation (or highest computation speed) of the synthesised circuit.
Perform a simulation to show that the circuit cannot produce correct results when the Min_Pulse constant is less that the worst case delay.

Fig. 4. Example waveform for the Adder_Subtractor_8bit showing how a given input vector is computed over time generating wrong results until all signals have propagated through the circuit. 
6. Report
Project report starting with the template sheets of paper, scanned figures, file listings, docx, pptx, or any other resources. Take care of the computer folders where the project are archived.
7. Prototyping
Use training boards and perform laboratory measurements to verify how the circuit works.
Other similar projects on arithmetic combinational circuits
 This is an example of a structural hierarchical 7bit 2C multiplier build in Proteus using a network of cascadable 1bit multipliers and other logic circuits.
 Here you are many HADES Java applets on arithmetic circuits.
 Parity generators, multipliers, dividers, ones counter, code converters, etc.
 A summary of projects proposed in the P4 to study basic standard arithmetic circuits. This is the P_Ch1 proposed organization and assessment checklist. Adapt it conveniently to class instructions and follow the given template.
 There are hundreds of web pages and videos over the internet on binary arithmetic circuits. And every book on the subject has several chapters on arithmetic circuits because they are fundamental blocks of computers.
Fig. 5. A dedicated processor representing the Arithmetic and Logic Unit (ALU) as the core of the datapath structure. Source: Hwang, E., Digital Logic and Microprocessor Design with VHDL, CLEngineering, 2005. 
Examples of midterm exams (Exa_1)
 1718Q1. This is the exam EX1 (pdf) and here you are a Proteus simulation to experiment the way it works, and a possible solution. The Gray_Bin_Converter (Chip1) in Minilog format.
 1718Q2. This is the exam EX1 (pdf) and a discussed solution. This is the Problem 1 truth table in Minilog format.
 1617Q2. This is an example exercise IT1 (pdf) that contains many concepts develop since now through P1 .. P4. This is the Proteus file, the truth table in Minilog and the results when simplifying by PoS. This is the discussion on the problem solved some years ago.
 1617Q2. This is another similar exercise IT1r (pdf). The truth table, the Minilog result, and the symbol in Proteus that can be simulated attaching this "jed" to the AM22V10 sPLD. This is a possible VHDL file (question 5), and this is the ispLEVER Classic report where you see the pin connections after synthesising the circuit.