UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL


P4: Arithmetic operations for signed integer numbers in 2C and measuring circuit propagation delay and speed


Resources in lectures and labs:  L4.1L4.2, Lab4, L3.1 Project objectives

Highlighted project: 8-bit adder-subtractor for signed integers. How fast is this circuit?

1. Specifications

Design an 8-bit adder and subtractor in two's complement with zero (Z), sign (S) and overflow (OV) flags using VHDL and multiple-file hierarchical structural approach (plan C2). Discus the symbol (below in Fig 1). Write its truth table. How long is it? Draw a timing diagram example.


Fig. 1. a) Symbol of an 8-bit 2C  adder/subtractor.



 Run this project solved in Proteus 8-bit 2C adder and subtractor and try to visualise better how operates and how the two's complemented data looks like.

truth table
b) Example of truth table combinations. Int_add_subt_8bit works only with signed integer operands.
Timing diagram

c) Timing diagram sketch showing how the Int_Add_Subt_8bit performs several additions and subtractions using two's complement signed integer operands. It is ready for translation as a VHDL testbench stimulus process.

Circuit's maximum processing speed. Once the circuit works and is tested functionally as usual, perform a gate-level simulation to determine the circuit's propagation delay in a given transition and also the circuit's maximum speed of operation using the timer analyser tool.

 VHDL design flow shows gate-level simulation as the 5th design step to save time before making real measurements in the lab uploading the configuration file to the prototyping board. For instance, two different experiments can be carried out:

  • Measure computation speed of circuits such Adder_1bit or Adder_Subt_8bit targeted for the same CPLD or FPGA. Logically, a larger circuit composed of more levels of gates generates larger propagation delays and calculates slower.
  • You can also discuss how the electrical characteristics of the synthesised circuit is dependent on technology changing project's target chip. Measure maximum speed of operation of the Adder_Subt_8bit using:

    • Two of our Xilinx boards: try the FPGA Spartan-3E XC3S500E-FG320 and the the CPLD XC2C256-TQ144 - 7 (chips).

    • Two of our Intel boards, try the FPGA Cyclone IV EP4CE115F29C7N and the CPLD MAX II EPM2210F324C3 (chips).


Other hierarchical multiple-file arithmetic 2C projects:

- Int_mult_8bit in Proteus, 8-bit multiplier for  integer numbers in two's complement

- Int_Comp_8bit, 8-bit comparator for integer numbers in two's complement


2. Planning circuits using hierarchical multiple-component structure

 Example plan where an Adder_8bit from P3 with some modifications is used for both, additons and subtractions.

Fig. 2. Proposed plan.

- Study how the zero flag (Z) works. Is it the same as in Adder_8bit?

- Study how the overflow logic (OV) works and why it is designed (notes).

- Count and name all the components and VHDL files  involved in the project. Name the project folder: 


3. Development

Once you have completed the planning of the project in Fig. 1, you can start the synthesis process. Write down the VHDL files translating the plans above using components and signals modifying a convenient seed circuit. For instance, these circuits may suit you: Adder_1bit.vhd, Adder_4bit.vhd, Adder_8bit.vhd, Int_add_subt_8bit.vhd. You see that the 4-bit and 8-bit adders are slightly modified because the overflow flag OV is generated using the most significant carry signals.

Run the EDA tool to synthesise the circuit. Print and comment the RTL schematic. Is it like what you had sketched in the plan? 

Fig. 3. Example of RTL diagram schematic interpreted by the EDA synthesis tool. 

At this level, it is very interesting for you to play with technology schematics as well. They are the real synthesised circuits for a given target chip. In addition to the technology view there is also the chip planner tool where you can locate exactly the logic cells used in the design.

Tech view  
logic elements

Fig. 4. Example of technology implementation in an FPGA Cyclone IV EP4CE115F29C7 from Intel. In this example circuit, 21 logic elements are used of the 114480 available. Remark how no memory registers/latches are used because it is a combinational circuit (Chapter I) instead of a sequential system (Chapter II). In this sense, if your implementation contains registers or inferred latches it means that it is wrong and you must debug your architecture to find mistakes in VHDL files.


4. Testing (functional simulation)

The testbench fixture containing the main ideas cand concepts involved in this schematic is represented in Fig. 5.

testbench fixture
Fig. 5. Testbench VHDL schematic.

Convert the initial timing diagram sketch in Fig. 1c into a VHDL testbench like in file Int_add_subt_8bit_tb.vhd writing input activity process and Min_Pulse constant in the template produced by the EDA tool. It is a good idea adapting test vectors from Adder_8bit in P3. Use several positive and negative numbers as inputs. Test both additions and subtractions. Check overflow and zero situations.

Run the EDA VHDL simulator and demonstrate how the circuit works adding comments to the printed sheet of paper containing the waveforms.

functional sim

Fig. 6. Example test with some input vectors. A, B and R are 2C numbers. 


5. Testing (gate-level simulation) and timing analyser measurements

Run a gate-level simulation to measure the worst case delay and the maximum speed of operation (or highest computation speed) of the synthesised circuit.

Perform a simulation to show that the circuit cannot produce correct results when the Min_Pulse constant is less that the worst case delay.  

propagation delay measurement

Fig. 7. Example waveform for the Int_add_subt_8bit showing how a given input vector is computed over time generating wrong results until all signals have propagated through the circuit. Picture taken from the tutorial.

Use timing analyser tool to determine worst-case scenario, and thus the maximum speed of calculations for a given target chip. For instance, considering Intel chips, which is faster, MAX II CPLD EPM2210F324C3  or Cyclone IV FPGA EP4CE115F29C7N ?


6. Report

It is required a handwritten original project report containing sections 1 - 2 - 3 - 4 -5, scanned figures with annotations, file listings, diagrams, sketches or any other resources. Theory stuff to comprehend how the circuit works may be included in section 1 on specifications. 


7. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit being designed works for real.

Fig. 8. Some switches are used for A(7..0) and B(7..0) operarands. One button OP selects add or substract. Eight green LED are used to represent signed integer results R(7..0), and three red LED are used for displaying flags.