UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

P4

P5: analysis of circuits based on flip-flops, latches and logic gates

P6


Resources in lectures and labs:  L5.1, Lab5 L5.2 on memories Project objectives

Highlighted project: asynchronous circuit based on T_FF

1. Specifications

1. Analyse Circuit_Async represented in Fig. 1 based on flip-flops.

Method 1: Analyse the circuit in Fig 1 drawing a timing diagram sketch to see how each flip-flop evolves in time. Determine what kind of output codes are generated each CLK cycle. What is the function of this circuit?

Method 2: Capture the circuit in Proteus and run simulations to check whether your paper analysis is correct. Use the logic analyser instrument to represent both inputs and outputs in function of time.

Method 3: Capture the circuit in VHDL as a plan C2 structure, synthesise it and run a simulation testbench to represent all inputs and outputs in time in a waveform logic diagram.

Symbol

Fig. 1. Symbol and schematic of the asynchronous circuit to be analysed. CLK is a rectangular wave of TCLK period. Clear direct (CD) is a single pulse any time the user like to initialise the circuit. This classic chip DM74LS93/92/90 is an example on how flip-flops and logic gates are used to build digital circuits with memory capacity

Circuit_async

 

2. Demonstrate the drawbacks associated with asynchronous designs running gate-level simulations. Pay attention to the outputs zooming around CLK transitions and explain what happens from one output code to the next. 

 


Other similar analysis problems: As usual in CSD, before attempting this analysis project, we need to review materials, theory and other analogous examples of asynchronous and synchronous circuits.

- Use these tutorials to learn about specifications for 1-bit memory cells: D_FF, JK_FF (and also RS_FF), T_FF.

- Circuit_Async2 includes a video recording.

- Circuit_Async3

- Circuit_Async4

- Circuit_Sync1

- Circuit_Sync2

 

2. Planning (up to three strategies to analyse the circuit)

analysis planning

Fig. 3. We get solutions comparing results form three methods.

 

3. Method 1 development 

General procedure and paper work for analysing circuits based on flip-flops.

a)  Study how a single flip-flop works. Imagine values for control input T (or D, JK, RS) and try to obtain outputs applying function tables.

b) Identify the number of CLK signals in the circuit. Is it asynchronous or synchronous? To draw the timing diagram, go step by step advancing in time (which means advancing by TCLK periods (circuit's time resolution).

c) Be sure to identify what T (or D, JK, RS) input values are sampled at the CLK's rising edge. To do it, consider the small tCO (in the range of ns) associated to each output transition. Add text discussing what is happening after each CLK active.

d) Once the timing diagram is completed, determine the number of states and what is the binary output for each state.

 

In this circuit, there are only T_FF, and they work as explained in its tutorial. ç

This circuit contains four CLK signals. It is asynchronous, because rising edges are not going to happen exactly at the same time, thus complicating the analysis.

In this circuit, T inputs are always sampled to be '1', as shown in Fig. 4, and the small tCO is not going to be important.

The circuit is generating 16 different states: 15 --> 14 --> 13--> .... --> 1 -->0 ---> 15 --> ... It is a down counting sequence  in binary radix-2. Therefore, this is 4-bit down counter running in continuous mode.

Timing diagram

Fig. 4. Example of timing diagram and analysis discussion. The complication of this circuit is related to the several CLK signals CLK, CLK1, CLK2, CLK3 delayed each other TCO, and thus false output codes are generated at signal transitions.

Testing is this case means comparing results from other methods.


3. Method 2 development 

Project location:

C:\CSD\P5\Circuit_async\Proteus\(files)

Draw your Circuit_async.pdsprj and simulate in Proteus. Verify your solution using the logic analyser instrument. This a Proteus circuit to play with flop-flops as if we were in the laboratory building such circuits for real using classic 4000 CMOS series. When picking parts from the library to mount your circuit, do this initialization --> Tool --> Global Annotator --> Total. Example adaptation Circuit_async.pdsprj.

Circuit_Capture
Downcounting

Fig. 5. Example of circuit captured in Proteus with logic analyser results. 

Testing is this case means comparing results from other methods.

 


3. Method3 development 

Project location:

C:\CSD\P5\Circuit_async\VHDL\(files)

The internal architecture of the circuit proposed in Fig. 1 has to be fully annotated as in Fig. 6 before developing the VHDL project. This is a plan C2 project of two files.

Circuit_async

Fig. 6. Circuit fully annotated and ready for translation to VHDL.

 Write down the VHDL file corresponding the Circuit_async.vhd from the schematic above in Fig. 6. The flip-flop description in VHDL is available in its tutorial T_FF.

Syntesise the project Circuit_Async_prj.

Inspect and analyse the RTL schematic generated by the synthesiser EDA tool as shown in Fig 7.

RTL

Fig. 7. RTL produced by the synthesiser.

 

Inspect and analyse the technology schematic generated by the synthesiser EDA tool as shown in Fig 8.

tech

Fig. 8. Technology schematic to be tested using gate-level simulations. In red is represented the CLK path from one T_FF to the next. Note how four D_FF registers are used, one per T_FF.

 

4. Method 3 testing (functional)

Fig. 9 shows the generalised VHDL testbench schematic that we have in mind to run simulations for our sequential systems under test. Remark the significant change replacing Min_Pulse constant by CLK_Period to define from now on time resolution.

Fig. 9. General testbench fixture for sequential systems, including at least two stimulus processes: one for the CLK and another for the remaining input ports.

Fig. 10 represents the inputs required in this experiment. A periodic CLK waveform of rectangular shape, for instance with a duty cycle = 25% and a clear direct CD pulse that can be repeated when necessary to initialise again the circuit. Make all the timing relative to the constant CLK_Period, that is the equivalent in Chapter 2 to the Chapter 1 contant Min_Pulse.

CLK and CD signals

Fig. 10. CLK and CD activity to be described in the testbench processes. From this activity the simulator will calculate outputs. Normal operation of the circuit can be inspected for example setting CLK_Period = 4 us. And detailed time measurements on signal transitions can be performed setting CLK_Period = 40 ns when testing the real technology view synthesised circuit for a given target chip (FPGA or CPLD).

 

Start the testbench template and add CLK and inputs activity translating input signals in the timing diagram. Thus, to test sequential systems at least two stimulus processes will be required: the CLK process and another process for all the other inputs. This is an example testbench file Circuit_async_tb.vhd.

Functional simulation. Run the EDA VHDL tool and demonstrate how the circuit works adding comments to the printed sheet of paper containing the waveforms.

Functional

Fig. 11. Waveforms from functional simulation. This circuit looks like that is acting as a 4-bit binary counter in radix-2.

 

5. Method 3 testing (gate-level)

Gate-level simulation. Run the EDA VHDL tool using the same test bench and demonstrate CLK to output propagation delays (tCO) and calculate the maximum frequency of operation. 

all

Fig.12. Results from a gate-level simulation zooming all the test time to see that it works as expected.

 

transition

Fig. 13. Results from a gate-level simulation focusing a single transition in ns time resolution window.

 


Extra (recommended): enhance the circuit in Fig. 1 as shown in Fig. 14, adding a decoder Dec_4_16 to convert 4-bit output codes to 16-bit one-hot codes for better observing how poorly is performing in transitions from one code to the next.

Circuit_async_onehot

Fig. 14. Symbol of the modified circuit with 16-bit one-hot vector output Q(15..0).

In this way, it is even easier to visualise the problems at CLK transitions of this circuit. New project location at:

C:/CSD/P5/Circuit_async_onehot/(files)

Circuit_async_onehot
  Fig. 15. Schematic of the asynchronous circuit with one-hot outputs designed to observe the poor performance of asynchronous circuits based on CLK rippling or using CLK as another logic signal to control flip-flops.

 

This is VHDL description for the decoder Dec_4_16.vhd component translating this plan B (drawing). Thus, the project resulting from the translation of Fig. 15 schematic Circuit_async_onehot.vhd will generate one-hot outputs.

Circuit RTL

Fig. 16. RTL produced by the synthesiser of the project with one-hot outputs.

 

 Similar waveforms in the logic analyser can be observed running Counter_onehot_16bit_async using a similar testbench Circuit_async_onehot_tb.vhd

Gate-level view  

Fig. 17. Results from a gate-level simulation focusing a single transition in the Circuit_async_onehot.

 

Compare Fig. 17 with gate-level results from a canonical FSM-based syncronous circuit (glitch, propagation time, etc.)


6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works.

 

7. Report

It is required a handwritten original project report containing sections 1 - 2 - 3 - 4 - 5, scanned figures with annotations, file listings, diagrams, sketches or any other resources. Theory to comprehend how the circuit works may be included in section 1 on specifications or annexed. 

 

What goes next?   

- Thus, in the end, if these asynchronous circuits behave so poorly, what is the right way to design reliable sequential circuits? The answer in next P6: Synchronous canonical sequential circuits based on FSM architecture.