upc eetac_1

Project P5 on 1-bit memory cells, synchronicity (CLK) and finite state machines (FSM)

Asynchronous latch type 74279A and synchronous flip-flop type HEF4027B

1. Specifications (understanding the problem)

A. Design a synchronous 1-bit memory cell type JK flip-flop (JK-FF). It can be used to store/save/write/register a 1-bit of information, as a frequency divider by 2 or as the basic block to implement digital counters and data registers. As you see in Fig. 1 function table, at the CLK's rising edge, the output value will depend on the inputs J and K and also on the previously stored value. 


Fig. 1. Symbol, function table and example timing diagram of a JK flip-flop. Clear direct (CD) is the asynchronous reset. Be aware how the J and K inputs has to be stable before the sampling edge, because if not, the output is unpredictable. (Visio)


B. Perform a gate-level simulation of the circuit to measure its CLK-to-output time (TCO) and thus, the maximum frequency of operation for a given target chip.

Fig. 2. Flip-flop setup, hold and clock-to-output timing parameters. Source. For a given technology, TCO determines the minimum CLK period, as the outputs must be stabilised before applying another CLK rising edge.


Learning materials:

- This is the structural description of a RS latch using NOR gates VHDL, testbench. Notes from wikipedia: RS latch cell.

- These are some class notes on: 1) The RS latch, 2) the RS latch with enable, 3) the RS flip-flop, 4) the D-type flip flop. This is an example circuit in Proteus. The commercial RS latch is the 74LS279 and the gated D latch is the 74LS75 (also called transparent latch).

- The data flip-flop (D_FF) using a single-file behavioural VHDL. This device is used as the memory cell in the FSM state register. 

- Tutorial on how to design a toggle flip-flop (T_FF) using a FSM topology. Therefore, you can design the JF flip flop using the same plan.

- Tutorial on the analysis of an asynchronous circuit, the strategy that is unreliable. All our circuits will be synchronous following the FSM architecture.


2. Planning (devising a strategy to solve the problem)

First of all, let's study the basics of the 1-bit memory devices (asynchronous latches and synchronous flip-flops). How are they designed and work.

And, once the theory understood, let us apply the FSM methodology to build and test the JK_FF as a single file project. This procedure is going to be repeated in all the FSM projects.

1) Figure out the state diagram. Number of states and conditions of transitions. Write the outputs at each state in parenthesis and using another colour.

2) Particularise the general FSM topology in Fig. 3 to this problem. Number of bits for the current and next state coding (r). [ r = number of states if one-hot; r = (1/log 2)·log (number of states) if binary or Gray]. To which block is connected every input and output port?

3) State register. We'll use always the same VHDL code description.

4) CC2. Truth table, and flow chart if a behavioural description is used, which is normally the best idea because Boolean algebra is left to the synthesiser. The CC2 is required to calculate the outputs at each state.

5) CC1. Truth table, and flow chart if a behavioural description is used, which is normally the best idea because Boolean algebra is left to the synthesiser. CC1 is required to calculate the next state to go after the CLK's rising edge.

6) Project folder location and file name (JK_Flip_Flop.vhd):




Fig. 3. Topology and description of the FSM used in CSD. (Visio).

Finally, once the circuit works after solving a functional simulation, perform the gate level simulation to obtain time measurements.

3. Development (carrying out the plan)

Write down the VHDL file corresponding the the T_FF after having translated the flow charts of the CC1 and CC2 and copied the state register. Copy and adapt a previous example. 

The name of the source file is JK_Flip_Flop.vhd. Run the EDA tool to synthesise the circuit and print and comment the RTL schematic. Check the number of registers (DFF) used in the target chip. In this simple example, the answer has to be a single DFF register.

Start the test bench template and add the CLK and inputs activity translating the timing diagram. Thus, to test sequential systems at least two stimulus processes will be required: the CLK and all the other inputs. Make all the timing relative to the CLK_Period constant, which is the equivalent in Chapter 2 to the Chapter 1 Min_Pulse.


4. Testing (and looking back and forward...)

Complete a sample test bench file named JK_Flip_Flop.vht translating a timing diagram like the one represented above in the specifications into a CLK and input signals stimulus processes.

1) Functional simulation. Run the EDA VHDL tool and demonstrate how the circuit works adding comments to the printed sheet of paper containing the waveforms.

2. Gate-level simulation. Run the EDA VHDL tool using the same test bench and demonstrate the CLK to output delays and the maximum frequency of operation for a given CPLD or FPGA target chip.


Fig. 4. VHDL testbench. Let's use different processes to drive the inputs and the CLK.


5. Report

Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources


6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works.

Other similar projects on sequential circuits

- Here you are some guided exercises (1) and (2) on sequential systems that will give you an idea of the possibilities and applications of sequential designs.

- A summary of projects proposed in the P5 to study basic 1-bit memory cells.


Other materials of interest


- Flip-Flops are the basic building block of digital systems. They are fully documented everywhere.

- For instance, the Lattice Semiconductor CPLD ispMACH4128V TQFP100 contains 128 macrocells. Each macrocell (Fig. 5) includes a configurable register D-FF along with some logic and control functions.

Fig. 5. ispMACH macrocell