UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 2 problems

      - A2.1 -

-- Analysis of a synchronous circuit




1. Specifications

Fig. 1 represents a circuit based on D_FF found browsing Internet. Let us name it Circuit_DFF. In Fig. 2 we have adapted it as usual to our conventions and naming style so that we can use our tools to analyse it.

Input enable is not necessary because it is simply a CLK blocker when '0' preventing the circuit advancing in time (in P7 we will present better methods for halting, stopping or freezing a circuit activity without interfering the special CLK signal).

Circuit to be analised

Fig. 1. Circuit based on D_FF.

Determine how does the circuit work, meaning finding the vector output Q(2..0) using the three methods:

Method 1. Handwritten analysis.

Method 2. Proteus capture and simulation.

Method 3. VHDL synthesis and test. What is the maximum CLK frequency when picking a target chip MAXII EPM2210F324C3?


Fig. 2. Circuit_DFF to be analysed using our three methods.