UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

PLA1_2

Q&A

PLA2: Circuit design using single-VHDL file plans A and B

PLA3

Lab2
NOTE: This post-lab assignment must be solved only after having studied in detail and completed successfully lab session Lab2 in your computer because you will copy and adapt materials from it.

Specifications (DeMUX_8 plan A)

Design a DeMUX_8 similar to the classic 74HCT138 chip in a programmable logic device (PLD) target chip following structural plan A using our VHDL design flow and EDA tools for developing and testing. The circuit symbol and its truth table is represented in FIg. 1. This PLA is adapted from problem D1.6.

Symbol DeMUX_8

Fig. 1. DeMUX_8 symbol and truth table. Select channel input S(2..0) is defined as vector.

Project location:

 C:\CSD\P2\PLA2\DeMUX_8A\(files)

 

Specifications (DeMUX_16 plan A)

Design a DeMUX_16 similar to the classic 74HCT154 chip in a programmable logic device (PLD) target chip following structural plan A using our VHDL design flow and EDA tools for developing and testing. The circuit symbol and its truth table is represented in FIg. 1. This PLA is adapted from problem D1.7.

Symbol DeMUX_16

Fig. 1. DeMUX_16 symbol and truth table. Select channel input S(3..0) and outptus Ch(15..0) are defined as vectors.

Project location:

 C:\CSD\P2\PLA2\DeMUX_16A\(files)

 

 

Specifications (DeMUX_8 plan B)

Design a DeMUX_8 similar to the classic 74HCT138 chip in a programmable logic device (PLD) target chip following behavioural plan B using our VHDL design flow and EDA tools for developing and testing. The circuit symbol and its truth table is represented in Fig. 1. This PLA is adapted from problem D1.6.

Symbol DeMUX_8

Fig. 1. DeMUX_8 symbol and truth table. Select channel input S(2..0) is defined as vector.

Project location:

 C:\CSD\P2\PLA2\DeMUX_8B\(files)

 

Specifications (DeMUX_16 plan B)

Design a DeMUX_16 similar to the classic 74HCT154 chip in a programmable logic device (PLD) target chip following behavioural plan B using our VHDL design flow and EDA tools for developing and testing. The circuit symbol and its truth table is represented in Fig. 1. This PLA is adapted from problem D1.7.

Symbol DeMUX_16

Fig. 1. DeMUX_16 symbol and truth table. In this symbol. Select channel input S(3..0) and outptus Ch(15..0) are defined as vectors.

Project location:

 C:\CSD\P2\PLA2\DeMUX_16B\(files)

 

 
Example of individual assignments
  Circuit Design plan Target chip  
Est. 1 DeMUX_8 A MAX 10
Est. 2 DeMUX_16 B Cyclone IV
Est. 3 DeMUX_16 A MAX II
Est. 4 DeMUX_8 B MAX 10
··· ··· ··· ···