Project P3 on arithmetic circuits in radix-2: adder, comparator, etc. |
Designing an 8-bit binary adder (type 74HCT283)
Multiple-file hierarchical VHDL design (Plan C2)
1. Specifications
Using the VHDL design plan C2, invent an 8-bit binary adder (Adder_8bit) based on simpler chips of the same kind like 4-bit (Adder_4bit) and 1-bit (Adder_1bit) adders. Synthesise it for a target CPLD/FPGA device and test it using VHDL EDA tools.
Plan a 4-bit adder using two alternative internal architectures: Circuit 1: ripple-carry and Circuit 2: carry-lookahead techniques.
Teamwork and project management.
Fig. 1. Symbol of an 8-bit binary adder. (Visio). Draw its truth table and sketch a timing diagram showing how it performs several 8-bit additions. |
Learning materials:
- To learn about the plan C2 (the design flow (pdf, visio) includes multiple VHDL files to define the entity):
- Use the method of decoders (MoD) and the method of multiplexers (MoM) to build logic functions. For example, solve the circuits in P1.
- LAB#4. Use this tutorial on how to build an 8-channel multiplexer (MUX_8) using structural hierarchical schematic with multiple VHDL files. This top schematic can be used as a seed project to copy and adapt to any other hierarchical design.
- In this GA#4 you can find even more examples of circuits solved by means of the plan C2.
- To learn about arithmetic circuits for radix-2 numbers:
- This is a project 8-bit adder in Proteus. Run it and visualise how the input and output operands looks like.
- Explain the characteristics of the most usual binary codes.
- Solve basic arithmetic operations on numbers in binary system (or radix-2, base-2): addition, comparison, multiplication, subtraction, etc.
- Read the Chapter 4 of this book Digital logic and microprocessor design with VHDL by prof. Enoch O. Hwang.
- Tutorial on how to design a 1-bit full adder Adder_1bit using several structural and behavioural approaches.
- LAB#4. Tutorial on how to design a 4-bit adder Adder_4bit based on ripple carry technique. Plan C2. It can be used as a seed project to copy and adapt to any other large design.
- Tutorial on how to design a 4-bit adder Adder_4bit based on a carry-lookahead technique. Plan C2. This is a commercial standard 4-bit adder 74HCT283.
- Tutorial on how to design a 1-bit expandable comparator Comp_1bit using the structural plan A. The idea on how to organise a larger comparator, for instance a Comp_4bit is based on using the auxiliary inputs Gi, Ei, Li which allow cascading circuits of the same kind, as in the problem 3.9. This is a commercial standard 4-bit comparator 74F85.
- The same tutorial for the Comb_1bit but using a plan C2 based on the MoM.
- This is a Proteus example of an 8-bit multiplier (Mult_8bit) for radix 2 numbers build using a network of cascadable 1-bit multipliers (Mult_1bit). Plan C2.
2. Planning
Even though, as in the previous projects, we have the two possibilities, structural and behavioural, let's design this P3 structurally and hierarchically using COMPONENTS and SIGNALS accordingly to the Plan C2; therefore as a multiple VHDL file project. Learning how to use components is the key point of the CSD course because it'll allow you to plan very large and complicated circuits hierarchically, as you saw in Proteus schematics, where you can go "Cntl+C" to the child sheet of each entity subcircuit. Thus, from now on, the subcircuits will become components. and the wires and cables signals.
In order to learn how to translate a project based on the plan C2 to VHDL, better if we start with the tutorial MUX_8 above.
Because this design is complex, this is the proposed general organisation to reach the Adder_8bit:
[Project A or Project B] --> [Project C or Project D]--> Project E
Therefore, better if we go step by step bottom-up starting from the most simple component: the 1-bit full adder.
Project Adder_1bit:
Project A: Plan. Let's design an Adder_1bit using the method of multiplexers. How many VHDL files are required? Name them all. You can use this method of implementing truth tables to design any kind of combinational circuit. .
<disk>/CSD/P3/PA/(files)
Project B: Plan. Let's design an Adder_1bit using the method of decoders. How many VHDL files are required? Name them all. You can use this method of implementing truth tables to design any kind of combinational circuit.
<disk>/CSD/P3/PB/(files)
Project Adder_4bit:
Project C: This is a ripple carry Adder_4bit. The Adder_1bit component can contain any architecture such as the Project A or the Project B above or any other structural or behavioural description from this tutorial.
<disk>/CSD/P3/ripple/(files)
Project D: This is a carry-lookahead Adder_4bit. So, both the ripple carry and the carry-lookahead adders have the same entity definition but different internal architectures. And so, they will have different performance when implemented in a CPLD chip. This design is similar to the standard chip type 74HCT283.
<disk>/CSD/P3/lookahead/(files)
Project Adder_8bit:
Project E: (plan). Design a 8-bit adder using a hierarchy of components.
<disk>/CSD/P3/Adder_8bit/(files)
Organise the work in cooperative groups to be able to handle this set of projects.
3. Development
Indeed here you develop up to 5 different projects: PA or PB, PC or PD and PE in the usual way: writing the schematics in VHDL. One project at a time. Indeed, you can use always this Adder_4bit.vhd (or this MUX_8.vhd) to adapt any project from now on. Run the EDA tool to synthesise the circuit. Print and comment the RTL and technology schematics.
1. Adder_1bit. Write the project files and run the projects PA or PB. Print the RTL and also the technology view. Discuss, comment and annotate the schematics identifying components.
Only when the PA or PB are tested you can continue:
2. Adder_4bit. Write the project files and run the projects PC or PD: Print the RTL and also the technology view. Discuss, comment and annotate the schematics identifying components.
- These files can be used to solve the project PD: Adder_4bit, Carry_Generator.
Only when the PC or PD are tested you can continue:
3. Adder_8bit. Write the project files and run the project PE, Print the RTL and also the technology view. Discuss, comment and annotate the schematics identifying components.
- These files can be used to solve the project PE: Adder_8bit
4. Testing
We have to test and verify the projects sequentially in the usual way: using the EDA simulator and a VHDL-based testbench fixture. One project at a time. This is a sequence: One you have tested the PA / PB, you can plan-develop and test the PC / PD, and so on. The reason is because the PA or the PB are going to be used as components in the design of the PC or PD, so they must be verified before using them in other projects. That's the idea of a COMPONENT as a reusable chip.
To convert the initial timing diagram sketch into a VHDL testbench (for instance Adder_8bit_tb.vhd) write inputs activity starting with a few vectors and the Min_Pulse constant in the template produced by the EDA tool. It's a good idea to adapt the test vectors of the 4-bit adder to obtain a file like this: Adder_8bit_tb.vhd.
Run the EDA VHDL simulator and demonstrate how the circuit works adding comments to the printed sheet of paper containing the waveforms.
5. Report
Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources.
The idea of a report at this level has to be clear for you now: technical document that demonstrates the way you have designed a given product. Furthermore, it allows you to prepare an oral presentation because it includes everything to generate high quality slides. Simple class notes and conventional exercices may be right for passing exams, but using your project reports you'll be able to teach your peers as if you had become a class instructor.
6. Prototyping
Use training boards and perform laboratory measurements to verify how the circuit works.
Other similar projects on arithmetic combinational circuits
- Here you are many HADES Java applets on arithmetic circuits.
- Tutorial on how to design an 4-bit ones counter using a hierarchical structural approach based on implementing logic functions using the method of decoders. This tutorial includes also a gate-level simulation example to determine the maximum speed of operation of the synthesised circuit into the CPLD/FPGA.
- Tutorial on how to design an 8-bit ones counter using a hierarchical structural approach cascading simpler components of the same kind. This tutorial includes also a gate-level simulation example to determine the maximum speed of operation of the synthesised circuit into the CPLD/FPGA.
Other materials of interest
- Q & A.
- There are several former units and exercises on arithmetic circuits (1), (2), as well as hundreds of web pages and videos over the internet. Every book on the subject has several chapters on arithmetic circuits because they are fundamental blocks of computers.
- Exams, questions, problems and projects.