Project P3 on arithmetic circuits in radix2: adder, comparator, etc. 
8bit binary adder
and multiplefile VHDL (hierarchical) design (Plan C2)
1. Specifications
Solve basic arithmetic operations on numbers in binary system (or radix2, base2): addition, comparison, multiplication, subtraction, etc. Example standard chips: adder 74HCT283, ALU 74AS181, comparator 74F85. and carry lookahead generator 74HCT182
Explain the characteristics of the most usual binary codes.
Plan structural hierarchical schematics and develop them in VHDL language using multiplefile projects. for instance, design a 8bit binary adder (Adder_8bit) based on simpler chips of the same kind like 4bit (Adder_4bit) and 1bit (Adder_1bit) adders. Synthesise it for a target CPLD/FPGA device and test it using VHDL EDA tools.
Plan a 4bit adder using two alternative layouts: Plan 1: ripplecarry and Plan 2: carrylookahead techniques.
Use the hierarchical methods of decoders and multiplexers to build logic functions. For instance, design the Adder_1bit using this approach.
Teamwork and project management.
Fig. 1. Symbol of an 8bit binary adder. (Visio). Draw its truth table and sketch a timing diagram showing how it performs several 8bit additions. 
Learning materials:
 These are high quality slides to study the basics on arithmetic circuits (ref). Or instead, read the Chapter 4 of this book Digital logic and microprocessor design with VHDL by prof. Enoch O. Hwang.
 Tutorial on how to build a 8channel multiplexer (MUX8) using structural hierarchical schematic with multiple VHDL files. This is the Plan C2 studied in P2, and can be used as a seed project to copy and adapt to any other large design.
 How does the method of decoders for implementing logic functions work? The Circuit_C solved using this method (1).
 How does the method of multiplexers for implementing logic functions work? The Circuit_C solved using this method and a MUX4 (2), finish it.
 Tutorial on how to design a 1bit full adder (adder_1bit) using several structural and behavioural approaches.
 Tutorial on how to design a 4bit adder (Adder_4bit) based on ripple carry technique, a component like the standard 74HCT283 using a structural hierarchical with multiple VHDL files. It can be used as a seed project to copy and adapt to any other large design.
 This is a project report on the design of a 1bit comparator arithmetic circuit that can be used as a building block for larger comparators and other circuits (for instance in the Problem 4.3). The 4bit commercial comparator chip 74LS85 can be studied to figure out how to chain such devices. Source files for designing it as a flat circuit based on SoP equations: Comp_1bit.tbl, the output from minilog Comp_1bit.min, the translation to VHDL Comp_1bit.vhd, and the test bench example Comp_1bit_tb.vhd.
 Tutorial on how to design an 4bit ones counter using a hierarchical structural approach based on implementing logic functions using the method of decoders. This tutorial includes also a gatelevel simulation example to determine the maximum speed of operation of the synthesised circuit into the CPLD/FPGA.
 Tutorial on how to design an 8bit ones counter using a hierarchical structural approach cascading simpler components of the same kind. This tutorial includes also a gatelevel simulation example to determine the maximum speed of operation of the synthesised circuit into the CPLD/FPGA.
2. Planning
Even though, as in the previous projects, we have the two possibilities, structural and behavioural, let's design this P3 structurally using COMPONENTS and SIGNALS accordingly to the Plan C2; therefore as a multiple VHDL file project. Learning how to use components is the key point of the CSD course because it'll allow you to plan very large and complicated circuits hierarchically, as you saw in the Proteus schematics, where you can go "Cntl+C" to the child sheet of each entity subcircuit. Thus, from now on, the subcircuits will become components.
In order to learn how to tranalate a project based on the plan C2 to VHDL, better if we start with the tutorial MUX_8 above.
This may be the proposed general for this P3. Therefore, better if we go step by step bottomup starting from the most simple component: the 1bit full adder.
Project Adder_1bit:
Project A: Plan. Let's design an Adder_1bit using the method of multiplexers. How many VHDL files are required? Name them all. You can use this method of implementing truth tables to design any kind of combinational circuit. .
<disk>/CSD/P3/PA/(files)
Project B: Plan. Let's design an Adder_1bit using the method of decoders. How many VHDL files are required? Name them all. You can use this method of implementing truth tables to design any kind of combinational circuit.
<disk>/CSD/P3/PB/(files)
Project Adder_4bit:
Project C: This is a ripple carry Adder_4bit. The Adder_1bit component can contain any architecture such as the Project A or the Project B above or any other structural or behavioural description in this tutorial.
<disk>/CSD/P3/ripple/(files)
Project D: Let's build a 4bit carrylookahead adder. So, both the ripple carry and the carrylookahead adders have the same entity definition but different internal architectures. And so, they will have different performance when implemented in a CPLD chip. This design is similar to the standard chip type 74HCT283.
<disk>/CSD/P3/lookahead/(files)

Fig. 2. The idea of the carrylookahead to reduce the propagation time in addition operations. Source: Wikipedia, and this book: Ercegovac, M., Lang, T., Moreno, J. H., "Introduction to Digital Systems", John Wiley & Sons, 1999), which also includes high quality slides. Chapter 10 is on arithmetic circuits. Here you'll find the set of equations that define the Carry_generator component.

Thus, this in Fig. 3 is the proposed plan for the circuit. How many VHDL files are required? Name them all.

Fig. 3. The plan to design the 4bit carrylookahead adder with the structural internal architecture of the component Carry_generator and its equations for obtaining all the carries with only 3levelsofgates.

Project Adder_8bit:
Project E: (plan). Design a 8bit adder using a hierarchy of components.
<disk>/CSD/P3/Adder_8bit/(files)
Organise the work in cooperative groups to be able to handle this set of projects.
3. Development
Indeed here you develop up to 5 different projects: PA or PB, PC or PD and PE in the usual way: writing the schematics in VHDL. One project at a time. Indeed, you can use always this Adder_4bit.vhd (or this MUX_8.vhd) to adapt any project from now on. Run the EDA tool to synthesise the circuit. Print and comment the RTL and technology schematics.
1. Adder_1bit. Write the project files and run the projects PA or PB. Print the RTL and also the technology view. Discuss, comment and annotate the schematics identifying components.
Only when the PA or PB are tested you can continue:
2. Adder_4bit. Write the project files and run the projects PC or PD: Print the RTL and also the technology view. Discuss, comment and annotate the schematics identifying components.
 These files can be used to solve the project PD: Adder_4bit, Carry_Generator.
Only when the PC or PD are tested you can continue:
3. Adder_8bit. Write the project files and run the project PE, Print the RTL and also the technology view. Discuss, comment and annotate the schematics identifying components.
 These files can be used to solve the project PE: Adder_8bit
4. Testing
We have to test and verify the projects sequentially in the usual way: using the EDA simulator and a VHDLbased testbench fixture. One project at a time. This is a sequence: One you have tested the PA / PB, you can plandevelop and test the PC / PD, and so on. The reason is because the PA or the PB are going to be used as components in the design of the PC or PD, so they must be verified before using them in other projects. That's the idea of a COMPONENT as a reusable chip.
To convert the initial timing diagram sketch into a VHDL testbench (for instance Adder_8bit_tb.vhd) write inputs activity starting with a few vectors and the Min_Pulse constant in the template produced by the EDA tool. It's a good idea to adapt the test vectors of the 4bit adder to obtain a file like this: Adder_8bit_tb.vhd.
Run the EDA VHDL simulator and demonstrate how the circuit works adding comments to the printed sheet of paper containing the waveforms.
5. Report
Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources.
The idea of a report at this level has to be clear for you now: technical document that demonstrates the way you have designed a given product. Furthermore, it allows you to prepare an oral presentation because it includes everything to generate high quality slides. Simple class notes and conventional exercices may be right for passing exams, but using your project reports you'll be able to teach your peers as if you had become a class instructor.
6. Prototyping
Use training boards and perform laboratory measurements to verify how the circuit works.
Other similar projects on arithmetic combinational circuits
 Here you are a similar project in Proteus, the 8bit adder and subtractor that will be used in P4. Run it and visualise how the input and output operands looks like.
 Here you are many HADES Java applets on arithmetic circuits.
 This is an example of a 8bit multiplier (Mult_8bit) for radic 2 numbers build using a network of cascadable 1bit multipliers (Mult_1bit).
 Comparators, number of ones counter, etc.
Other materials of interest
 There are several former units and exercises on arithmetic circuits (1), (2), as well as hundreds of web pages and videos over the internet. Every book on the subject has several chapters on arithmetic circuits because they are fundamental blocks of computers.
 Exams, questions, problems and projects.