UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL


P3: Arithmetic circuits in radix-2: adder, multiplier, comparator, etc. VHDL design plan C2: hierarchical structural modular multiple-file


Resources in lectures and labs:  L3.1, Lab3L3.2, L3.3 Project objectives

Highlighted project: 8-bit ones counter using plan C2

1. Specifications

Design a circuit to count the number of ones in its 8-bit input vector using a hierarchical approach.


Fig. 1. Symbol and examples from the truth table of the 8-bit ones counter.

This application can be used for example to count de number of free slots in a parking. Only the number of parked cars is important, not their current position in the parking.

Timing diagram

Fig. 3. Timing diagram sketch.

Inputs may be connected to contact switches, ultrasonic, radio or IR light sensors. Thus, they may be modelled imagining pushbuttons or switches as shown on Fig. 4. Outputs are represented in binary radix-2, however, it is easy to imagine a code converter from radix-2 to BCD to represent the number of ones in 7-seg displays. 


Fig. 4. Push button generating '0' and '1' for modelling digital sensors.

Propose a circuit that at the same time can be expanded to a larger number of inputs, for instance 32 or 64 bit.

Other hierarchical multiple-file VHDL projects (Plan C2):

Ones_counter_4bit, number of '1' in 4 inputs (MoD)  
Adder_1bit MoM (designed in Lab3 and Lab4) Adder_1bit MoD
Adder_4bit ripple carry (RC) Adder_4bit carry lookahead (CLA)
Adder_8bit (designed in Lab3) Adder_16bit (designed in Lab4)
Mult_8bit  (circuit captured in Proteus)  
MUX_8 Optional: this is the MUX_8 using plan C1.
Enc_10_4 using Enc_8_3  
Comp_1bit using the MoM Comp_1bit using the MoD (proposed in PLA3)
Comp_4bit chaining Comp_1bit components Comp_10bit chaining Comp_1bit
Rec. on Adder_2bit Rec. on Dec_3_8
Large code converters such as radix-2 --> BCD (Bin_BCD_9bit) or BCD --> radix-2 (BCD_bin_6digit) can be implemented using hierarchical schematics from 74184/74185 datasheet.  

Other arithmetic components using flat single-file VHDL projects (Plan A or plan B):

- Comp_1bit plan A Comp_1bit plan B
- Comp_4bit plan A  
- Adder_1bit plan A Adder_1bit plan B

Other assignments (design problems D1.1, D1.2, ...)


2. Planning

Organise the architecture of this circuit using smaller components. How many VHDL files will be required?


Fig. 5. Planning the application using components and signals.

Therefore, this design requires three bottom-up steps:

1.- Design the project of the 4-bit ones counter using any convenient plan (A, B or C2). For example this is the design using plan C2 and the MoD: Ones_counter_4bits.

2.- Design the project of the 4-bit adder. Here you have two versions of this circuit base on plan C2: Adder_4bit ripple carry (RC), Adder_4bit carry lookahead (CLA).

3.- Translate the circuit in Fig. 5 to VHDL to be the top schematic.

Project location:



3. Developing the project using EDA tools

- This is the Fig. 5 translation to VHDL ones_counter_8bit.vhd.  

- Run a EDA project to synthesise the circuit for a target chip, for instance MAXII EPM2210F324C3.

Hiearchical plan C2 RTL

Fig. 6. RTL view.

This design uses 11 logic elements.



Fig. 7. Hierarchical component structure, technology view and resources used.


4. Testing the design (functional)

The test bench fixture is used for organising the VHDL simulation project in ModelSim.


Fig. 8. Testbench fixture.

Translate the sketch of an example timing diagram to a VHDL test bench. This is an example from which to copy constant Min_Pulse and the input stimulus ones_counter_8bit_tb.vhd.

Discuss results on waves from the logic analyser tool.

Functional results

Fig. 9. Funcional results.


5. Testing and validating the design (gate-level)

Each PLD(FPGA has its electrical characteristics, thus the final performance will be related to the particular target chip specifications.

Let the synthesiser generate the EDA netlist file ones_counter_8bit.vho. And also the delay file: ones_counter_8bit.sdo.

simulation files

VHDL translation of the technology schematic

Fig. 10. Translation to VHDL of the technology view.

Let us start a gate-level (timing) simulation project with the library work_gate_level. Delay file must be assigned to the testbench entity.

Region for the SDO delay file

Fig. 11. SDO delay file assigned to the region.

Run the logic analyser to observe the circuit behaviour at a given transition. As you see in Fig. 12, it takes the circuit 8.26 ns to obtain the correct count of ones when switching from input "01110101" to "11111111". And in between, there are several wrong output values while the signals are propagating through the chip structure.

Delay measurement at a given transition

Fig. 12. Example of gate-level simulation where we can inspect the delay of the outputs at a given inputs transition.

EDA tool timing analyser available in Quartus Prime allows the measurement of the worst-case scenario propagation time (tP) and thus calculate the maximum speed of operation for the target technology.

In this example the maximum processing speed is 109 MHz (more than 100 millions of operations -counting the number of ones in the input vector- per second).

Timing analyser

Fig. 13 Timing analyser results.


6. Report

Follow this rubric for writing reports.


7. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works. Each specific board requires some kind of adaptation, for instance active voltage levels, multiplexed display systems, etc.

This DE10-Lite page explains how to install drivers and run an application.

Assign pins with the pin planner spreadsheet.

Generate the output SOF file and run the programmer.