﻿ Digital Circuits and Systems - Circuits i Sistemes Digitals (CSD) - EETAC - UPC
 Bachelor's Degree in Telecommunications Systems and in Network Engineering

## Filtering and synchronising inputs: push-button debouncer

Basics on synchronous FSM

1. Specifications

Let us design a digital filter to clean the noisy signal generated when pressing and releasing a mechanical key or pushbutton. When clicking and releasing a key, the electrical signal generates a random number of ones and zeros (signal bouncing) that must be filtered out in order to interface correctly a digital circuit. Additionally, the idea is to synchronise the key signal (an asynchronous input) to the system CLK, so that it can be correctly sampled. This phenomena is sampled correctly in the range of 100 Hz.

 Fig. 1. Example of the waveforms describing the phenomena. Clicking a mechanical key has to generate a clean single pulse. (visio)

Thus, we aim to design the circuit in Fig. 2 using a FSM strategy and with this conditions:

- After clicking the push button (which is active low), the QA and QB will go high ('1') only after that 3 consecutive '0' have been sampled. This situations means that the signal is already stable with someone currently pressing the key.  QA will be assessed only for one clock pulse.

- Once the pushbutton is released, QB will go low after 2 consecutives '1' sampled. This means that duration of the QB pulse (for instance counting the number of CLK pulses while the signal is high) is a measurement of the time in which the key (or the sensor) is pressed (or active).

 Fig. 2. The circuit to be designed have two outputs: QA to produce a single pulse, and QB to generate a pulse that last as long as the key is being pressed.

Before attempting the design of the debouncing filter, it is better to pay attention on how the idea of sampling signals works for a simple key or push-button . The questions to solve are: what is the best sampling frequency? why it is necessary a FSM acting as a digital filter instead of a simpler D_FF for this function of conditioning or interfacing a push-button?

 Fig. 3. This is the kind of signal generated when clicking and releasing a button.

 Fig. 4. Sampling with a D_FF. A sampling frequency that is too high with respect to the physical phenomena of clicking and realising a key will not filter the signal correctly. Signal bounces will be captured and thus, many (random) digital pulses will be generated every time that the key is clicked and released. Precisely, the opposite is what is required in a digital oscilloscope, for instance running at 2 Gs/s (2 gigasamples per second), a perfect digitalisation or acquisition of the analogue signal at the 500 ps CLK period time scale.

 Fig. 5. Sampling with a D_FF. A sampling frequency that is too low with respect to the physical phenomena of clicking and releasing a key may not be able to detect the phenomena.

2. Planning

Let's infer the state diagram so that the system is able to memorise the sequence of zeros and ones that will produce the outputs QA and QB.

 Fig. 3. The state diagram.

Let's obtain the truth tables of the CC1 and CC2 combinational circuits, so that they can be easily translated to VHDL.

3. Development

This is the debouncing_filter.vhd VHDL code

Let's see if the synthesiser interprets correctly this FSM descriptions producing the RTL picture in Fig.4.

 Fig. 4. The RTL schematic.

 Fig. 5. Number of registers used in the synthesis of the circuit.

4. Testing

This is a sample test bench file debouncing_filter_tb.vhd.

1) Functional simulation. Run the EDA VHDL tool and demonstrate how the circuit works adding comments to the printed sheet of paper containing the waveforms.

 Fig. 6. Example of a timing diagram to show how the circuit works.

5. Report

Project report starting with the template sheets of paper, scanned figures, file listings, docx , pptx, or any other resources

6. Prototyping

Use training boards and perform laboratory measurements to verify how the circuit works.

Other materials of interest

- Christoffersen, J., "Switch bounce and how to deal with it", All about circuits, 2015.

- A reference from the MIT: Study of a level-to-pulse converter. Why to synchronise input signals?

 Fig. 7. Detecting and synchronising an external input.