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Bachelor's Degree in Telecommunications Systems and in Network Engineering |
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CSD products |
This is a detailed list of materials to help you to study and design projects and thus, solve the course without complications. Please, get used to asking us as many questions as necessary.
| Analysis and design tutorials | Analysis and design assignments | Prototypes | Exam 1 | Exam 2 | Questions and assessment |
Chapter 1 analysis of circuits based on logic gates:
| AT1.1 | Circuit_C Highlighted P1 | AT1.2 | Circuit_W (L1.3, Lab 1.1) |
| AT1.3 | Circuit_W (Lab 1.2) | AT1.4 | Circuit_K |
| AT1.5 | Circuit_P | AT1.6 | Circuit_Q |
Chapter 2 analysis of synchronous and asynchronous circuits based on flip-flops and logic:
| AT2.1 | Circuit_Async | AT2.2 | Circuit_Sync1 |
| AT2.3 | Circuit_Async2 (Highlighted P5 project) | AT2.4 | Circuit_Async4 |
| Analysis and design tutorials | Analysis and design assignments | Prototypes | Exam 1 | Exam 2 | Questions and assessment |
Chapter 1 and 3 design projects of combinational circuits
In Chapter 3 these circuits are used to learn basic digital input and output.
| Plan A: structure, equations | Plan B: behavioural, truth table | Plan C2: hierarchical structure | |
| DT1.1 | Circuit_W (L1.4) | ||
| DT1.2 | Circuit_C Highlighted P1 | ||
| DT1.3 | Circuit_K | Circuit_K | Circuit_K |
| DT1.4 | Circuit_P | Circuit_PQ | Circuit_PQ |
| DT1.5 | Circuit_Q |
| Plan A: structure, equations | Plan B: behavioural, truth table | Plan C2: hierarchical structure | |
| DT2.1 | MUX_8,(Lab 2) | MUX_8, (Lab 2) | MUX_8 Optional demo: MUX_8 using plan C1 |
| DT2.2 | MUX_16 | ||
| DT2.3 | DeMUX_16 | ||
| DT2.4 DT9.1 |
Dual_MUX_4 | Dual_MUX_4 Dual_MUX_4 (μC I/O basics) (Lab 9) |
Dual_MUX_4 |
| DT2.5 | Quad_MUX_2 / Quad_MUX_4 | ||
| DT2.6 | MUX_DeMUX lab prototype | ||
| DT2.7 | Dec_3_8 | Dec_3_8 | Rec. on Dec_3_8 |
| DT2.8 | Dec_4_16 | Dec_4_16 | |
| DT2.9 | Hex_7seg_decoder Highlighted P2 | Hex_7seg_decoder Dec_hex_7seg | |
| DT2.10 | Enc_10_4 | Enc_10_4 | Enc_10_4 using Enc_8_3 |
| DT2.11 | Tank_level_meter | Tank_level_meter | |
| DT2.12 | Bin_BCD_6bit | Bin_BCD_6bit includes the DM74185 | |
| DT2.13 | BCD_bin_mod40 |
| Plan A: structure, equations | Plan B: behavioural, truth table | Plan C2: hierarchical structure | |
| DT3.1 | Bin_BCD_9bit | ||
| DT3.2 | Bin_BCD_16bit | ||
| DT3.3 | Comp_1bit | Comp_1bit | Comp_1bit using the MoM |
| DT3.4 | Comp_4bit | Comp_4bit | |
| DT3.5 | Comp_10bit | ||
| DT3.6 | Adder_1bit | Adder_1bit | Adder_1bit MoD Adder_1bit MoM, (Lab 3) |
| DT3.7 | Rec. on Adder_2bit | ||
| DT3.8 | Ones_counter_8bit Highlighted P3 Ones_counter_4bit |
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| DT3.9 | Adder_4bit carry lookahead (CLA) Adder_4bit ripple carry (RC) |
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| DT3.10 | Adder_8bit, (Lab 3) | ||
| DT3.11 | Adder_16bit, (RC) (Lab 4.1) Adder_16bit, (CLA) (Lab 4.1) |
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| DT3.12 | Mult_9bit | ||
| DT9.2 DT11.1 |
Adder_BCD_1digit (P9) (design phase #1) Adder_BCD_1digit_LCD (design phase #2) |
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| Plan A: structure, equations | Plan B: behavioural, truth table | Plan C2: hierarchical structure | |
| DT4.1 | (advanced VHDL course) | (advanced VHDL course) | Int_add_subt_8bit Highlighted P4 |
| DT4.2 | |||
| DT4.3 | Int_Mult_9bit | ||
| DT4.4 | ALU_9bit lab prototype |
Chapter 2 and 3 design tutorials on FSM
| Plan C1 for FSM, single VHDL file, three processes | Plan C1 adaptation to C language | ||
| DT6.1 | D_FF, D-type flip-flop | ||
| DT6.2 | JK_FF, JK flip-flop (also an RS-flip-flop) | ||
| DT6.3 | T_FF, Toggle flip-flop | ||
| DT6.4 | Matrix_encoder_16key Highlighted P6 project | DT10.4 | Matrix_encoder_16key |
| DT6.5 | Light_control, classroom luminaries, (Lab 6) | ||
| DT6.6 | LED bicycle torch | ||
| DT6.7 | Debouncing_filter, low-pass filter and synchroniser. | DT12.12 | Debouncing_filter, PIC18F, bare-metal Debouncing_filter, PIC18F, MCC, DEE |
| DT6.8 | Traffic light controller | ||
Chapter 2 and 3 design tutorials on counters and registers
| Plan X: FSM, state enumeration | Plan Y: FSM, large number of states | Plan C2: hierarchical structure | ||
| DT7.1 DT10.2 |
Counter_BCD_1digit | Counter_BCD_1digit | ||
| Counter_BCD_1digit, (Lab 10), (design phase #1) | ||||
| DT11.3 | Counter_BCD_1digit_LCD (design phase #2) | |||
| DT12.3 | Counter_BCD_1digit_LCD_TMR0 (design phase #3) where TMR0 as counter replaces INT0. | |||
| DT10.3 |
Counter_mod_1572,(Lab 10) Counter_mod1572 |
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| DT7.2 | Counter_mod12 | Counter_mod12, (Lab 7) | Counter_mod12,(Lab 7) | |
| DT7.3 | Counter_mod16 | (versatile chip) | ||
| DT7.4 | counter_BCD_2digit.pdsprj (modulo 100) in Proteus, plan C2, chaining two 1-digit BCD counters | |||
| DT7.5 | Hour_counter Highlighted P7 project | |||
| DT7.6 | Counter_BCD_mod60 (seconds) | |||
| DT7.7 | Counter_BCD_MMSS (minutes, seconds) | |||
| DT7.8 | Data_reg_4bit | |||
| DT7.9 | Data_reg_1bit | |||
| DT7.10 | Shift_reg_4bit | (versatile chip) | ||
| DT7.11 | Barrel_3_shift_reg_21bit | |||
| DT7.12 | MDS: Multiplexed display system | |||
| DT7.13 | PWM Dimmer architecture TMR2 | |||
| DT10.4 | Johnson_sequencer_mod12 (design phase #1) | |||
| DT11.4 | Johnson_sequencer_mod12_LCD (design phase #2) | |||
| DT12.4 | Johnson_sequencer_mod12_LCD_TMR0 (design phase #3) | |||
Chapter 2 and 3 design tutorials on dedicated processors
| DT8.1 | CLK_Generator | ||
| DT8.2 | Timer_MMSS Highlighted P8 project |
Timer_MMSS | |
| DT8.3 | Mult_4bit serial multiplier | ||
| DT8.4 | Adder_4bit serial adder | ||
| DT10.1 | Design phase #1 | Serial_transmitter | |
| DT11.2 | Design phase #2 | Serial_transmitter_LCD | |
| DT12.1 | Design phase #3 | Serial_transmitter_LCD_TMR0 | |
| DT12.2 | Design phase #4 | Serial_transmitter_LCD_TMR2 | |
| DT8.5 | USART universal serial async receiver &transmitter |
USART | |
| DT8.6 | Add_accum_BCD_2digit adder and accumulator | ||
| DT8.7 | Real-time clock HH:MM:SS in Proteus | ||
| DT12.5 | Design phase #1 | Timer, (Lab 11) | |
| DT12.6 | Design phase #2 | Timer_LCD, (Lab 11) | |
| DT12.7 | Design phase #3 | Timer_LCD_TMR0, (Lab 11) | |
| DT12.8 | Design phase #4 | Timer_LCD_TMR2 | |
| DT12.9 | Temp_meter Arduino, DEE | ||
| DT12.10 | Tap_control Arduino, DEE | ||
| DT12.11 | Blinking_LED PIC18F, bare-metal Blinking_LED PIC18F, MCC, DEE Blinking_LED Arduino, DEE |
| Analysis and design tutorials | Analysis and design assignments | Prototypes | Exam 1 | Exam 2 | Questions and assessment |
Chapter 1 analysis assignments (circuits with logic gates)
| A1.1 | Circuit_L | A1.2 | Circuit_U |
| A1.3 | Circuit_VT | A1.4 | Circuit_M |
| A1.5 | Circuit_N | A1.6 | Circuit_G |
| A1.7 | Circuit_R | A1.8 | Circuit_Z |
| A1.9 | Circuit_Y |
Chapter 2 analysis assignments (circuits with flip-flops and logic gates)
| A2.1 | Circuit_E (sync) | A2.2 | Circuit_A (async) |
| A2.3 | Circuit_D (async) | A2.4 | Circuit_I (async) |
| A2.5 | Circuit_F (sync) | A2.6 | Circuit_B (async) |
| A2.7 | Circuit_C (async) | A2.8 | Circuit_G (async) |
| A2.9 | Circuit_H (async) |
| Analysis and design tutorials | Analysis and design assignments | Prototypes | Exam 1 | Exam 2 | Questions and assessment |
Chapter 1 and 3 design assignments
| D1.1 | B3.1 | Wind compass | D1.2 | B3.2 | 9's complementer for BCD arithmetic operations |
| D1.3 | B3.3 | 5-bit ones counter | D1.4 | B3.4 | From P1: Circuit_VT, Circuit_G, Circuit_U |
| D1.5 | B3.5 | 12-to-4 encoder | D1.6 | B3.6 | Water tank level meter (9 sensors) |
| D1.7 | B3.7 | 2-digit multiplexed 7-segment display | D1.8 | B3.8 | 5-bit Gray to binary and binary to Gray converters |
| D1.9 | B3.9 | 4-bit shifters (A) and barrel shifters (B) | D1.10 | B3.10 | 4-bit binary to Johnson and Johnson to binary converters |
| D1.11 | B3.11 | Sel _add_subt_comp_10bit | D1.12 | B3.12 | 16-bit comparator for integer numbers |
| D1.13 | B3.13 | 3-digit BCD subtractor using Subt_1bit | D1.14 | B3.14 | 9-bit parity generator, parity checker |
| D1.15 | B3.15 | BCD_bin_3digit, code converter | D1.16 | B3.16 | Bin_BCD_9bit, code converter |
| D1.17 | B3.17 | 3-digit BCD adder/subtractor for unsigned numbers | D1.18 | B3.18 | ALU_12bit |
| D1.19 | B3.19 | Parking occupancy (32-bit ones counter) | D1.20 | B3.20 |
Chapter 2 and 3 design assignments
| D2.1 | D3.1 | CD player buttons | D2.2 | D3.2 | Stepper motor controller |
| D2.3 | D3.3 | LED rotator and sequencer (v. A, B, C) | D2.4 | D3.4 | Pattern detector (versions 1 and 2) |
| D2.5 | D3.5 | LED dimmer | D2.6 | D3.6 | Serial Mult_8bit - Simple calculator |
| D2.7 | D3.7 | Dumbwaiter or simple lift | D2.8 | D3.8 | Electronic keypad lock (versions A and B) |
| D2.9 | D3.9 | Water tank controller | D2.10 | D3.10 | Vending machine |
| D2.11 | D3.11 | Wireless IR TV remote control | D2.12 | D3.12 | Electronic roulette |
| D2.13 | D3.13 | Serial Adder_16bit | D2.14 | D3.14 | Traffic light controller |
| D2.15 | D3.15 | 16-key matrix encoder with handshake | D2.16 | D3.16 | Scale, A/D conversion |
| D2.17 | D3.17 | Shower stall automation | D2.18 | D3.18 | Morse code generator |
| D2.19 | D3.19 | Washing machine controller | D2.20 | D3.20 | Dot matrix indicator driver |
| D2.21 | D3.21 | Programmable timer (versions A, B and C) | D2.22 | D3.22 | Bit pattern generator |
| D2.23 | D3.23 | Ear buds control buttons | D2.24 | D3.24 | Rotation speed meter (tachometer) |
| Analysis and design tutorials | Analysis and design assignments | Prototypes | Exam 1 | Exam 2 | Questions and assessment |
Laboratory prototypes and PCB for soldering and measuring
Most of our laboratory tutorials are accompanied by prototypes sections describing how to run the applications on training boards. For instance:
- Circuit_W (Lab 1_2). Simple combinational circuit to follow the VHDL design flow implemented in the DE10-Lite board.
- Standard hexadecimal to 7-segment decoder (Dec_Hex_7seg) to discover the DE10-Lite features. Install the USB-Blaster driver to program the FPGA.
- MUX_DeMUX (Lab 2). Connecting standard combinational circuits and using laboratory measurements. Switches and LED are connected through the 40-pin expansion connector mounted in a KiCad PCB. Install Waveforms software to run and measure using our compact instrument VB8012.
- ALU_9bit (Lab 4_2). Arithmetic and logic operations and measurements. Switches and LED are connected through the 40-pin expansion connector mounted in a KiCad PCB.
- CSD_PICstick (Lab 10). Our training board for Chapter 3 projects based on microcontrollers.
Other prototypes for demonstrations using legacy boards.
| Analysis and design tutorials | Analysis and design assignments | Prototypes | Exam 1 | Exam 2 | Questions and assessment |
Sample questionnaire Q1_4 on P1, P2, P3 and P4 projects. Chapter I.
Sample questionnaire Q5_12 on P5, P6, P7, P8 projects (Chapter II), and P9, P10, P11, P12 projects (Chapter III).
Class activities are available at the end of each CSD lecture. Remember that each CSD project integrates all the previous ones.
| Analysis and design tutorials | Analysis and design assignments | Prototypes | Exam 1 | Exam 2 | Questions and assessment |
Continuous assessment of student achievement
CSD scheme of continuous assessment (grading sheet): 11 items, many of which, specially class activities, include weekly formative feedback and discussion. Your partial grades will be available and updated at Atenea platform.
- P_Ch1 => 15% of the final grade:
- Individual: PLA1 (30%)
- Group work: PLA2_3 (report + video, 50%) + PLA4 (20%)
- P_Ch2 => 6%:
- Group work: PLA6_7 (report + video, 100%)
- P_Ch3 => 9 %:
- Group work: PLA9 (30%) + PLA10_11 (work in progress + report + video, 70%)
- Classroom activities => 1.2%
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| Web activa des de 09/2001, @ F. J. Robert, Web editat amb Microsoft Expression Web 4. El contingut és un complement als materials d'estudi del curs Circuits i Sistemes Digitals disponibles al campus digital Atenea. Llicència:Reconeixement 4.0 Internacional de Creative Commons |