UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 1 problems

      - A1.8 -

Analysing Circuit_Z

Products

A1.7

A1.9

 Specifications

Using our analysis method I proposed in CSD lecture L1.3,  Boolean algebra, pen and paper, find the truth table of the circuit represented in Fig. 1. Name it as Circuit_R. Express the output as a sum of minterms and as a product of maxterms.

Circuit_Z

Fig. 1. Combinational circuit Z = f(K, C1, C0, P) and its symbol.

Deduce the circuit algebraic equation that corresponds to the circuit in Fig. 1.

Transform the algebraic expression to SoP (or PoS) using Boole algebra.

Transform SoP (or PoS) to a sum of minterms (or a product of maxterms). Draw the truth table. Express the truth table as a sum of minterms and as a product of maxterms.

Draw an example of timing diagram considering all binary combinations and a constant Min_Pulse = 1.76 μs. How long does it take to simulate all the combinations?

Project location to save your paper solution, class notes, pictures, theory, etc.:

C:\CSD\P1\Circuit_Z\algebra\(files)

Verify your results solving the same project using another analysis method.

 

Using our analysis method II (VHDL EDA synthesis and simulation tools from Intel, LAB1.2) find the circuit's symbol and truth table of the algebraic expression represented in Fig. 1.

Plan your analysis.

Use the following location to save your project:

C:\CSD\P1\Circuit_Z\proteus\(files)

Draw the circuit in Proteus adapting a similar one based on the same technology. Start drawing only two or three logic gates and run de simulation to see that you get no errors.

Proteus components library options:

 option #1.: LS-TTL

 option #2.: CMOS

Verify your results solving the same project using another analysis method.

 

Using our analysis method III (VHDL EDA synthesis and simulation tools from Intel, LAB1.2) find the circuit's symbol and truth table of the algebraic expression represented in Fig. 1.

Plan your analysis.

 Use the following location to save your project:

C:\CSD\P1\Circuit_Z\VHDL\(files)

Start writing the architecture of a very simple equation and run the synthesis and simulation to check that your software operates correctly.

Target chip options:

 option #1.: MAX II

 option #2.: MAX 10

 option #3.: Cyclone IV

Verify your results solving the same project using another analysis method.

 

Using our analysis method IV (WolframAlpha computer numerical engine, LAB1.1) find the circuit's symbol and truth table of the algebraic expression represented in Fig. 1.

Plan your analysis.

 Use the following location to save your project:

C:\CSD\P1\Circuit_Z\wolfram\(files)

Start writing in a text file "Circuit_Z_equ.txt" a very simple equation in WolframAlpha to check that the engine works correctly and you can interpret the results.  

Verify your results solving the same project using another analysis method.

 

NOTE: You better add theory, class-notes or other learning materials in section 1 on specifications in one of your projects.

Explain, discuss and try to locate in CSD lessons or laboratory tutorials the concepts and tools used in these PLA plans and developments, so that you are sure that these materials will help you to study and solve similar problems in Exam 1.