UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Chapter 2 problems

- D2.1 -

CD-MP3 player controller (FPGA -VHDL)

Products

 

D2.2

1. Specifications

Design phase #1: basic FSM

Our aim is to design a CD-MP3 player controller based on mechanical buttons and switches available on the front panel as pictured in Fig. 1. Other similar devices and applications have tactile screens or keypads.

The same project as an alternative design programming a μC is proposed in D3.1.

CD_Player sketch

Fig. 1. CD-MP3 player application and its symbol.

Buttons will be sampled at the system frequency fCLK indicated as an option in design phase #3. The pause LED L will be blinking when in pause. The output M to run the motor to spin de compact disc to read the audio files.

Draw an example of timing diagram.

Diagram

Fig. 2. Example timing diagram.

Find commercial devices where similar buttons control how the music is played (Hi-Fi audio chain, Bluetooth earbud, DVD player, etc.)?  

 

2. Planning ideas for the design phase #1

The planning is based on applying our FSM recipe in L6.1. This architecture is translated to VHDL as a plan C1 single file where the three main components are processes.

Let us propose a state diagram, and do it in two steps. For instance:

- Design step #1: Player with a single button Play/Pause. 

Project location:  C:\CSD\P6\MP3_player1\(files)

state diagram

Fig. 3. CD-MP3 player FSM state diagram for design step #1.

Therefore, only when this step #1 is completely developed and tested (1-2-3-4), you can enhance the basic state diagram considering additional buttons and switches.

- Design step #2: Player with buttons Play/Pause and Stop and also with the door switch Open.

state diagram

Fig. 4. CD-Mp3 player FSM state diagram for design step #2.

Project location:

 C:\CSD\P6\MP3_player2\(files)

Adapt the FSM architecture to this problem, naming and connecting all signals and inputs and outputs. 

Deduce how many D_FF are required when encoding FSM states using the following options and draw the state register memory:

Option #1: radix-2 (sequential)

Option #2: Gray

Option #3: Johnson

Option #4: one-hot

Draw the state register memory block.

Write the truth table of CC2 and CC1 and their equivalent behavioural interpretations (plan B) using flowcharts.

Write the FSM VHDL file.

Start a Quartus Prime synthesis project for one of the following programmable target chips:

Option #1: Cyclone IV EP4CE115F29C7

Option #1: MAX II EPM2210F324C3

Inspect and annotate the RTL and technology views. Check the number of D_FF synthesised in this application.

Generate a VHDL testbench fixture schematic. Translate the timing diagram sketch from the specifications into de corresponding stimulus processes.  

Run functional simulations to verify your design. Visualise as well in the wave timing diagram the internal states.

Run gate-level simulations to measure the propagation time CLK to output (tCO). Measure the minimum TCLK period or the maximum frequency of operation of the FSM.

 

Design phase #2: FSM + datapath

 Generate a confirming user action beep (a 1 s 1.4 kHz audible sound wave for 0.9 s) every time the user clicks play/pause. 

Enhance your device adding at least one of the following new features:

- To save battery, add operational resources to switch off the device when paused for 2 min.

- Indicate in seven-segment displays the time MM:SS the device is playing.

Project location:  C:\CSD\P7\MP3_player\(files)

 

Design phase #3: CLK_Generator

Design the CLK generator circuit from a 50 MHz quartz crystal oscillator to obtain all the clocking signals required to drive the application. Deduce the number of D_FF that the full project MP3_player will require.

Project location:  C:\CSD\P8\MP3_player\(files)

The options for the system CLK are:

Option #1: fCLK = 330 Hz

Option #2: fCLK = 220 Hz

Option #3: fCLK =  150 Hz