UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

PLA3

Q&A

PLA4: Gate-level and timing analyser measurements

PLA5

Lab4
NOTE: Learn how to perform gate-level simulations and how to measure using the timing analyser in this Lab4. This post lab assignment PLA4 must be solved only after having completed successfully the lab session; it consist in repeating all the concepts in another similar circuit.

Specifications

We will continue the project proposed in PLA3 developing the new VHDL design flow step #5: characterising how fast is the circuit for the given internal design architecture you solved in PLA3, and for a given target chip option.

This PLA4 is also a project in itself, as all the others, so plan it using several sections like A, B, C, D. The main theory content related to this PLA is in lecture L4.3.

You can use in gate-level simulations the same PLA3 testbench fixture and its VHDL file that were used in functional simulations.

Initial work:

Solve Lab4 in your computer to learn gate-level simulations and timing anaysler tool.

If your PLA3 circuit is not yet fully operational or were not correctly synthesised or tested, take some time to correct it. PLA3 sections 1-2-3-4 do not have to be reported again, explain only in an annex what was wrong and corrected. If your PLA3 is fully operational, perform more operations in binary, explain better the operands, results and flag.

Print and comment the technology view that now will be tested in this design step #5.

Developing and measuring:

Measure the propagation delay tPD in a given transition using gate level simulations. Draw an schematic indicating the operands that are switching and the expected results, both in decimal and also in binary.

Using the timing analyser, determine the maximum propagation delay tPD in a given transition.

Calculate the maximum speed (frequency) fMAX in which your circuit can operate. Draw an schematic indicating the operands that are switching and the expected results, both in decimal and also in binary.

You can repeat the measurements for two target chip options (technology):

 option #1: MAX II

 option #2 Cyclone IV

Final discussion:

Which technology is faster?

If instead of PLD and FPGA, we were designing using classic chips, how many levels of gates contain will contain your circuit? (To answer this question imagine that all your circuits are based on plan A and plan C2).

Demonstrate that the circuit does not calculate or operate correctly when Min_Pulse is shorter that the circuit's propagation delay.

Planning_1


Planning_2

Fig. 1. Concepts, ideas and planning the VHDL design flow step #5. Thus, if you PLA3 is working correctly, simply copy its structure (VHDL files) and its testbench file to the new location and rerun individually the synthesis & simulation processes adding the new section #5 on gate-level simulations and timing analyser tools. Do it for the two chip options and discuss results.

 

Example of individual assignments

Each student will continue and report individually the new step #5 of the project assigned to their cooperative group in PLA3.  Organise this PLA as a project, use the two programmable chips and discuss which one is faster. Answer the questions.

 

 

 

P_Ch1 marking grid for projects PLA1.1, PLA1.2, PLA2, PLA3 and PLA4

P_Ch1 => 10%      => PLA1.1 (10%) + PLA1.2 (10%) + PLA2 (20%) + PLA3 (group, report + video, 50%) + PLA4 (10%)

Work in progress assessments to be carried out in laboratory sessions (individual)
  PLA1.1 PLA1.2 PLA2 PLA4
1p 1p 2p 1p

Note Work in progress includes completing tutorials, sample reports, sketches, diagrams, discussions, Q & A, presentations, live demonstrations, results, measurements, etc.

 

PLA3 handwritten report and video presentation (group):
Video Report  
  2p 3p    

Notes on lab assessment: student grades are not simply reflecting report or video quality, but implicitly, they include laboratory attendance and punctuality, participation, Q & A, problem solving skills, active attitude and group work.