UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Planning

PLA1: Analysis of simple combinational circuits

Q&A    PLA2_3

Specifications

Study in detail and execute in your computer these tutorials L1.3, P1 analysis, Lab1_1, Lab1_2 before attempting this PLA.

Solve your assigned circuit applying the four analysis methods proposed in our plans.

Example of individual assignments
  Project number Circuit entity FPGA target chip Proteus libraries
Student 1 A1.7 Circuit_R MAX II LS-TTL
Student 2 A1.8 Circuit_Z Cyclone IV CMOS
Student 3 A1.9 Circuit_Y MAX 10 LS-TTL
Student 4 A1.7 Circuit_R Cyclone IV CMOS
... ... ... ... ....

Each analysis method requires to be placed in the project location indicated in the assignment.

Follow this rubric for writing reports. This assignment report will include at least sixteen sheets of paper (four complete and independent projects).  Add theory, class-notes or other learning materials only in one of the in (1) specifications in one of your projects.

NOTE for method III: ONLY when Lab1_2 tutorial is working in your computer, apply the following step by step tactical approach for developing correctly your project:

Step #1: Copy "Circuit_W.vhd" from our tutorial renaming it for instance "Circuit_U.vhd" and save it in the given project directory:  
                                                    C:\CSD\P1\Circuit_U\VHDL\

- Run the complete synthesis and verification projects. Select the given target chip, start a synthesis project, synthesise the circuit, display the RTL and technology views, generate the testbench skeleton, add stimulus signals and the constant Min_Pulse, and run ModelSim functional simulations to check that wave diagrams are as expected (in Circuit_W). Check that you have configured the ModelSim colour scheme because black colour background in pictures is not permitted (as it is a total waste of printing ink).

Step #2 (exactly in the same way that you simply draw a new gate in Proteus and run, or a simple equation in WolframApha and run to check): 

- Adapt the circuit's entity port names and equation in "Circuit_U.vhd". Add only one gate from your circuit, for example:

U <= not(not(X1) or X0));

- Re-synthesise, and re-run  until you get results.

- Add a few new gates and repeat until completing the analysis.