UPC EETAC Bachelor's Degree in Telecommunications Systems and in Network Engineering EEL

Planning

Q&A

PLA1: Analysis of simple combinational circuits

PLA2_3

P1 analysis, Lab1_1, Lab1_2

Specifications

Solve the circuit using the four analysis methods and the options indicated by your instructor.

Example of individual assignments
  Project number Circuit entity FPGA
target chip		 Proteus libraries
Student 1 A1.2 Circuit_U MAX II LS-TTL
Student 2 A1.6 Circuit_G Cyclone IV CMOS
Student 3 A1.3 Circuit_VT MAX 10 LS-TTL
Student 4 A1.2 Circuit_U Cyclone IV CMOS
... ... ... ... ....

Intel (Altera) FPGA target chip references are listed in this page on chip companies.

Each analysis method requires to be placed in the project location indicated in the assignment.

You can add theory, classnotes or other learning materials in section 1 on specifications in one of your projects.

Follow this rubric for writing reports. Because two complete projects are solved, this assignment will be is at least eight sheets of paper long report.  

 

NOTE: This post-lab assignment must be solved only after having completed successfully lab sessions Lab1_1 and Lab1_2 and also the highlighted tutorial P1 on analysis because you will adapt and apply materials and proceedings from them.

 

NOTE for method III: ONLY when Lab1_2 tutorial is working in your computer, apply the following step by step tactical approach for solving your project:

Step #1:
- Copy Circuit_W.vhd from our tutorial renaming it for instance Circuit_U.vhd and saving it in the given project directory:  C:\CSD\P1\Circuit_U\VHDL\

- Run the complete synthesis and verification projects. Select the given target chip, start a synthesis project, synthesise the circuit, display the RTL and technology views, generate the testbench skeleton, add stimulus signals and the constant Min_Pulse, and run ModelSim functional simulations to check that wave diagrams are as expected (in Circuit_W). Check that you have configured the ModelSim colour scheme because black colour background in pictures is not permitted (as it is a total waste of printing ink).

Step #2 (exactly in the same way that you simply draw a new gate in Proteus and run, or a simple equation in WolframApha and run to check): 
- Adapt the circuit's entity port names and equation in Circuit_U.vhd. Add only one gate from your circuit, for example:

U <= not(not(X1) or X0));

- Re-synthesise, and re-run  until you get results.

- Add a few new gates and repeat until completing the analysis.